2012-09-27 21:59:45 +02:00
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package uncore
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2012-04-03 21:03:05 +02:00
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import Chisel._
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2014-01-21 21:20:55 +01:00
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abstract class CoherenceAgent(implicit conf: TileLinkConfiguration) extends Module {
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2013-01-17 08:57:35 +01:00
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val io = new Bundle {
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2013-03-20 22:10:16 +01:00
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val client = (new TileLinkIO).flip
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val master = new UncachedTileLinkIO
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2013-08-12 19:36:44 +02:00
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val incoherent = Vec.fill(conf.ln.nClients){Bool()}.asInput
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2013-01-17 08:57:35 +01:00
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}
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}
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2013-08-02 23:55:06 +02:00
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case class L2CoherenceAgentConfiguration(tl: TileLinkConfiguration, nReleaseTransactions: Int, nAcquireTransactions: Int)
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class L2CoherenceAgent(bankId: Int)(implicit conf: L2CoherenceAgentConfiguration) extends CoherenceAgent()(conf.tl)
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2013-01-17 08:57:35 +01:00
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{
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2013-08-02 23:55:06 +02:00
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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// Create SHRs for outstanding transactions
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val nTrackers = conf.nReleaseTransactions + conf.nAcquireTransactions
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2013-08-12 19:36:44 +02:00
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val trackerList = (0 until conf.nReleaseTransactions).map(id => Module(new VoluntaryReleaseTracker(id, bankId))) ++
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(conf.nReleaseTransactions until nTrackers).map(id => Module(new AcquireTracker(id, bankId)))
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2013-01-17 08:57:35 +01:00
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2013-08-02 23:55:06 +02:00
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// Propagate incoherence flags
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2013-03-20 22:10:16 +01:00
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trackerList.map(_.io.tile_incoherent := io.incoherent.toBits)
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2013-01-17 08:57:35 +01:00
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2013-03-26 00:20:12 +01:00
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// Handle acquire transaction initiation
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2013-03-20 22:10:16 +01:00
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val acquire = io.client.acquire
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2013-01-29 01:39:45 +01:00
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val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_)
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2013-04-10 22:46:31 +02:00
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val block_acquires = any_acquire_conflict
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2013-01-17 08:57:35 +01:00
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2013-08-12 19:36:44 +02:00
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val alloc_arb = Module(new Arbiter(Bool(), trackerList.size))
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2013-03-20 22:10:16 +01:00
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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2013-05-22 02:19:07 +02:00
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alloc_arb.io.in(i).valid := t.acquire.meta.ready
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t.acquire.meta.bits := acquire.meta.bits
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t.acquire.meta.valid := alloc_arb.io.in(i).ready
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2013-03-20 22:10:16 +01:00
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2013-05-22 02:19:07 +02:00
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t.acquire.data.bits := acquire.data.bits
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t.acquire.data.valid := acquire.data.valid
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2013-01-17 08:57:35 +01:00
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}
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2013-05-22 02:19:07 +02:00
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acquire.meta.ready := trackerList.map(_.io.client.acquire.meta.ready).reduce(_||_) && !block_acquires
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acquire.data.ready := trackerList.map(_.io.client.acquire.data.ready).reduce(_||_)
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alloc_arb.io.out.ready := acquire.meta.valid && !block_acquires
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2013-01-17 08:57:35 +01:00
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// Handle probe request generation
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2013-09-11 01:15:41 +02:00
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val probe_arb = Module(new Arbiter(new LogicalNetworkIO(new Probe), trackerList.size))
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2013-03-20 22:10:16 +01:00
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io.client.probe <> probe_arb.io.out
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probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.probe }
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2013-01-17 08:57:35 +01:00
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2013-04-09 23:09:36 +02:00
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// Handle releases, which might be voluntary and might have data
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2013-03-20 22:10:16 +01:00
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val release = io.client.release
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2013-05-22 02:19:07 +02:00
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val voluntary = co.isVoluntary(release.meta.bits.payload)
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2013-01-29 01:39:45 +01:00
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val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_)
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2013-04-10 22:46:31 +02:00
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val block_releases = Bool(false)
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2013-08-12 19:36:44 +02:00
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val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)).lastIndexWhere{b: Bool => b}
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//val release_idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UInt(0)), release.bits.payload.master_xact_id) // TODO: Add merging logic to allow allocated AcquireTracker to handle conflicts, send all necessary grants, use first sufficient response
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val release_idx = Mux(voluntary, UInt(0), release.meta.bits.payload.master_xact_id)
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2013-03-20 22:10:16 +01:00
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for( i <- 0 until trackerList.size ) {
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val t = trackerList(i).io.client
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2013-05-22 02:19:07 +02:00
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t.release.meta.bits := release.meta.bits
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2013-08-12 19:36:44 +02:00
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t.release.meta.valid := release.meta.valid && (release_idx === UInt(i)) && !block_releases
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2013-05-22 02:19:07 +02:00
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t.release.data.bits := release.data.bits
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t.release.data.valid := release.data.valid
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2013-01-17 08:57:35 +01:00
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}
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2013-08-12 19:36:44 +02:00
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release.meta.ready := Vec(trackerList.map(_.io.client.release.meta.ready)).read(release_idx) && !block_releases
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2013-05-22 02:19:07 +02:00
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release.data.ready := trackerList.map(_.io.client.release.data.ready).reduce(_||_)
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2013-01-17 08:57:35 +01:00
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// Reply to initial requestor
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2013-09-11 01:15:41 +02:00
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val grant_arb = Module(new Arbiter(new LogicalNetworkIO(new Grant), trackerList.size))
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2013-03-20 22:10:16 +01:00
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io.client.grant <> grant_arb.io.out
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grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant }
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2013-01-17 08:57:35 +01:00
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// Free finished transactions
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2013-03-20 22:10:16 +01:00
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val ack = io.client.grant_ack
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trackerList.map(_.io.client.grant_ack.valid := ack.valid)
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trackerList.map(_.io.client.grant_ack.bits := ack.bits)
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2013-01-23 05:09:21 +01:00
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ack.ready := Bool(true)
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2013-01-17 08:57:35 +01:00
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// Create an arbiter for the one memory port
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2013-08-12 19:36:44 +02:00
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val outer_arb = Module(new UncachedTileLinkIOArbiterThatPassesId(trackerList.size))
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2013-03-20 22:10:16 +01:00
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outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.master }
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io.master <> outer_arb.io.out
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2013-01-17 08:57:35 +01:00
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}
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2013-01-29 01:39:45 +01:00
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2013-08-12 19:36:44 +02:00
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abstract class XactTracker()(implicit conf: L2CoherenceAgentConfiguration) extends Module with OuterRequestGenerator {
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2013-08-02 23:55:06 +02:00
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implicit val (tl, ln, co) = (conf.tl, conf.tl.ln, conf.tl.co)
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2013-01-17 08:57:35 +01:00
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val io = new Bundle {
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2013-03-20 22:10:16 +01:00
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val client = (new TileLinkIO).flip
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val master = new UncachedTileLinkIO
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2013-08-02 23:55:06 +02:00
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val tile_incoherent = Bits(INPUT, ln.nClients)
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2013-03-20 22:10:16 +01:00
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val has_acquire_conflict = Bool(OUTPUT)
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val has_release_conflict = Bool(OUTPUT)
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2013-01-29 01:39:45 +01:00
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}
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}
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2013-08-02 23:55:06 +02:00
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class VoluntaryReleaseTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgentConfiguration) extends XactTracker()(conf) {
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2013-09-10 19:54:51 +02:00
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val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(UInt(), 4)
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2013-08-16 00:27:38 +02:00
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val state = Reg(init=s_idle)
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2013-01-29 01:39:45 +01:00
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val xact = Reg{ new Release }
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2013-08-16 00:27:38 +02:00
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val init_client_id_ = Reg(init=UInt(0, width = log2Up(ln.nClients)))
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val release_data_needs_write = Reg(init=Bool(false))
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val mem_cmd_sent = Reg(init=Bool(false))
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2013-08-12 19:36:44 +02:00
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val cmd_to_write = Acquire(co.getUncachedWriteAcquireType, xact.addr, UInt(trackerId))
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2013-01-29 01:39:45 +01:00
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io.has_acquire_conflict := Bool(false)
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2013-05-22 02:19:07 +02:00
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.meta.bits.payload.addr) && (state != s_idle)
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2013-03-20 22:10:16 +01:00
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io.master.grant.ready := Bool(false)
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2013-05-22 02:19:07 +02:00
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io.master.acquire.meta.valid := Bool(false)
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io.master.acquire.meta.bits.payload := cmd_to_write
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2013-03-20 22:10:16 +01:00
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//TODO io.master.acquire.bits.header.dst
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2013-08-12 19:36:44 +02:00
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io.master.acquire.meta.bits.header.src := UInt(bankId)
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2013-05-22 02:19:07 +02:00
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io.master.acquire.data.valid := Bool(false)
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2013-08-12 19:36:44 +02:00
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io.master.acquire.data.bits.payload.data := UInt(0)
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2013-03-20 22:10:16 +01:00
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//TODO io.master.acquire_data.bits.header.dst
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2013-08-12 19:36:44 +02:00
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io.master.acquire.data.bits.header.src := UInt(bankId)
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2013-05-22 02:19:07 +02:00
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io.client.acquire.meta.ready := Bool(false)
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io.client.acquire.data.ready := Bool(false)
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2013-03-20 22:10:16 +01:00
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io.client.probe.valid := Bool(false)
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2013-05-22 02:19:07 +02:00
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io.client.release.meta.ready := Bool(false)
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io.client.release.data.ready := Bool(false) // DNC
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2013-03-20 22:10:16 +01:00
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io.client.grant.valid := Bool(false)
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2013-08-12 19:36:44 +02:00
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io.client.grant.bits.payload.g_type := co.getGrantType(xact, UInt(0))
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2013-03-20 22:10:16 +01:00
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io.client.grant.bits.payload.client_xact_id := xact.client_xact_id
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2013-08-12 19:36:44 +02:00
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io.client.grant.bits.payload.master_xact_id := UInt(trackerId)
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io.client.grant.bits.payload.data := UInt(0)
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2013-03-20 22:10:16 +01:00
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io.client.grant.bits.header.dst := init_client_id_
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2013-08-12 19:36:44 +02:00
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io.client.grant.bits.header.src := UInt(bankId)
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2013-01-29 01:39:45 +01:00
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switch (state) {
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is(s_idle) {
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2013-05-22 02:19:07 +02:00
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io.client.release.meta.ready := Bool(true)
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when( io.client.release.meta.valid ) {
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xact := io.client.release.meta.bits.payload
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init_client_id_ := io.client.release.meta.bits.header.src
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release_data_needs_write := co.messageHasData(io.client.release.meta.bits.payload)
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2013-08-12 19:36:44 +02:00
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mem_cnt := UInt(0)
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2013-01-29 01:39:45 +01:00
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mem_cmd_sent := Bool(false)
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state := s_mem
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}
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}
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is(s_mem) {
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when (release_data_needs_write) {
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2013-05-22 02:19:07 +02:00
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doOuterReqWrite(io.master.acquire,
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io.client.release.data,
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2013-07-25 08:22:36 +02:00
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cmd_to_write,
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2013-05-22 02:19:07 +02:00
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release_data_needs_write,
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2013-04-10 22:46:31 +02:00
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mem_cmd_sent,
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init_client_id_)
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2013-01-29 01:39:45 +01:00
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} . otherwise { state := s_ack }
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}
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is(s_ack) {
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2013-03-20 22:10:16 +01:00
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io.client.grant.valid := Bool(true)
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when(io.client.grant.ready) { state := s_idle }
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2013-01-29 01:39:45 +01:00
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}
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2013-01-17 08:57:35 +01:00
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}
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2013-01-29 01:39:45 +01:00
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}
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2013-01-17 08:57:35 +01:00
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2013-08-02 23:55:06 +02:00
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class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: L2CoherenceAgentConfiguration) extends XactTracker()(conf) {
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2013-09-10 19:54:51 +02:00
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(UInt(), 5)
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2013-08-16 00:27:38 +02:00
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val state = Reg(init=s_idle)
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2013-01-22 02:17:26 +01:00
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val xact = Reg{ new Acquire }
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2013-08-16 00:27:38 +02:00
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val init_client_id_ = Reg(init=UInt(0, width = log2Up(ln.nClients)))
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val release_data_client_id = Reg(init=UInt(0, width = log2Up(ln.nClients)))
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2013-01-17 08:57:35 +01:00
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//TODO: Will need id reg for merged release xacts
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2013-08-16 00:27:38 +02:00
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val init_sharer_cnt_ = Reg(init=UInt(0, width = log2Up(ln.nClients)))
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2013-01-29 01:39:45 +01:00
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val grant_type = co.getGrantType(xact.a_type, init_sharer_cnt_)
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2013-08-16 00:27:38 +02:00
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val release_count = if (ln.nClients == 1) UInt(0) else Reg(init=UInt(0, width = log2Up(ln.nClients)))
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val probe_flags = Reg(init=Bits(0, width = ln.nClients))
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2013-03-26 00:20:12 +01:00
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val curr_p_id = PriorityEncoder(probe_flags)
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2013-08-16 00:27:38 +02:00
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val x_needs_read = Reg(init=Bool(false))
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val acquire_data_needs_write = Reg(init=Bool(false))
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val release_data_needs_write = Reg(init=Bool(false))
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2013-08-12 19:36:44 +02:00
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val cmd_to_write = Acquire(co.getUncachedWriteAcquireType, xact.addr, UInt(trackerId))
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val cmd_to_read = Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId))
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2013-08-16 00:27:38 +02:00
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val a_w_mem_cmd_sent = Reg(init=Bool(false))
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val r_w_mem_cmd_sent = Reg(init=Bool(false))
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2013-08-02 23:55:06 +02:00
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val probe_initial_flags = Bits(width = ln.nClients)
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2013-01-23 05:09:21 +01:00
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probe_initial_flags := Bits(0)
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2013-08-02 23:55:06 +02:00
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if (ln.nClients > 1) {
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2013-01-17 08:57:35 +01:00
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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2013-03-26 00:20:12 +01:00
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val probe_self = Bool(true) //co.needsSelfProbe(io.client.acquire.bits.payload)
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2013-08-12 19:36:44 +02:00
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val myflag = Mux(probe_self, Bits(0), UIntToOH(io.client.acquire.meta.bits.header.src(log2Up(ln.nClients)-1,0)))
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2013-01-23 05:09:21 +01:00
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probe_initial_flags := ~(io.tile_incoherent | myflag)
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2013-01-17 08:57:35 +01:00
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}
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2013-05-22 02:19:07 +02:00
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io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.client.acquire.meta.bits.payload.addr) && (state != s_idle)
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io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.meta.bits.payload.addr) && (state != s_idle)
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io.master.acquire.meta.valid := Bool(false)
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2013-08-12 19:36:44 +02:00
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io.master.acquire.meta.bits.payload := Acquire(co.getUncachedReadAcquireType, xact.addr, UInt(trackerId))
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io.master.acquire.meta.bits.header.src := UInt(bankId)
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2013-05-22 02:19:07 +02:00
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io.master.acquire.data.valid := Bool(false)
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2013-08-12 19:36:44 +02:00
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io.master.acquire.data.bits.payload.data := UInt(0)
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io.master.acquire.data.bits.header.src := UInt(bankId)
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2013-03-20 22:10:16 +01:00
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io.client.probe.valid := Bool(false)
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2013-08-12 19:36:44 +02:00
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io.client.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UInt(0))
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io.client.probe.bits.payload.master_xact_id := UInt(trackerId)
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2013-03-20 22:10:16 +01:00
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io.client.probe.bits.payload.addr := xact.addr
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2013-08-12 19:36:44 +02:00
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io.client.probe.bits.header.dst := UInt(0)
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io.client.probe.bits.header.src := UInt(bankId)
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2013-03-20 22:10:16 +01:00
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io.client.grant.bits.payload.data := io.master.grant.bits.payload.data
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io.client.grant.bits.payload.g_type := grant_type
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io.client.grant.bits.payload.client_xact_id := xact.client_xact_id
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2013-08-12 19:36:44 +02:00
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io.client.grant.bits.payload.master_xact_id := UInt(trackerId)
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2013-03-20 22:10:16 +01:00
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io.client.grant.bits.header.dst := init_client_id_
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2013-08-12 19:36:44 +02:00
|
|
|
io.client.grant.bits.header.src := UInt(bankId)
|
|
|
|
io.client.grant.valid := (io.master.grant.valid && (UInt(trackerId) === io.master.grant.bits.payload.client_xact_id))
|
2013-05-22 02:19:07 +02:00
|
|
|
io.client.acquire.meta.ready := Bool(false)
|
|
|
|
io.client.acquire.data.ready := Bool(false)
|
|
|
|
io.client.release.meta.ready := Bool(false)
|
|
|
|
io.client.release.data.ready := Bool(false)
|
2013-03-20 22:10:16 +01:00
|
|
|
io.master.grant.ready := io.client.grant.ready
|
2013-01-17 08:57:35 +01:00
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
is(s_idle) {
|
2013-05-22 02:19:07 +02:00
|
|
|
io.client.acquire.meta.ready := Bool(true)
|
|
|
|
when( io.client.acquire.meta.valid ) {
|
|
|
|
xact := io.client.acquire.meta.bits.payload
|
|
|
|
init_client_id_ := io.client.acquire.meta.bits.header.src
|
2013-08-12 19:36:44 +02:00
|
|
|
init_sharer_cnt_ := UInt(ln.nClients) // TODO: Broadcast only
|
2013-05-22 02:19:07 +02:00
|
|
|
acquire_data_needs_write := co.messageHasData(io.client.acquire.meta.bits.payload)
|
2013-08-12 19:36:44 +02:00
|
|
|
x_needs_read := co.needsOuterRead(io.client.acquire.meta.bits.payload.a_type, UInt(0))
|
2013-01-23 05:09:21 +01:00
|
|
|
probe_flags := probe_initial_flags
|
2013-08-12 19:36:44 +02:00
|
|
|
mem_cnt := UInt(0)
|
2013-03-20 22:10:16 +01:00
|
|
|
r_w_mem_cmd_sent := Bool(false)
|
|
|
|
a_w_mem_cmd_sent := Bool(false)
|
2013-08-02 23:55:06 +02:00
|
|
|
if(ln.nClients > 1) {
|
2013-01-23 05:09:21 +01:00
|
|
|
release_count := PopCount(probe_initial_flags)
|
|
|
|
state := Mux(probe_initial_flags.orR, s_probe, s_mem)
|
2013-01-17 08:57:35 +01:00
|
|
|
} else state := s_mem
|
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_probe) {
|
2013-01-23 05:09:21 +01:00
|
|
|
when(probe_flags.orR) {
|
2013-03-20 22:10:16 +01:00
|
|
|
io.client.probe.valid := Bool(true)
|
|
|
|
io.client.probe.bits.header.dst := curr_p_id
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-03-20 22:10:16 +01:00
|
|
|
when(io.client.probe.ready) {
|
2013-08-12 19:36:44 +02:00
|
|
|
probe_flags := probe_flags & ~(UIntToOH(curr_p_id))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-05-22 02:19:07 +02:00
|
|
|
io.client.release.meta.ready := Bool(true)
|
|
|
|
when(io.client.release.meta.valid) {
|
2013-08-12 19:36:44 +02:00
|
|
|
if(ln.nClients > 1) release_count := release_count - UInt(1)
|
|
|
|
when(release_count === UInt(1)) {
|
2013-01-17 08:57:35 +01:00
|
|
|
state := s_mem
|
|
|
|
}
|
2013-05-22 02:19:07 +02:00
|
|
|
when( co.messageHasData(io.client.release.meta.bits.payload)) {
|
2013-04-10 22:46:31 +02:00
|
|
|
release_data_needs_write := Bool(true)
|
2013-05-22 02:19:07 +02:00
|
|
|
release_data_client_id := io.client.release.meta.bits.header.src
|
2013-04-10 22:46:31 +02:00
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
2013-04-30 03:47:37 +02:00
|
|
|
when (release_data_needs_write) {
|
2013-05-22 02:19:07 +02:00
|
|
|
doOuterReqWrite(io.master.acquire,
|
|
|
|
io.client.release.data,
|
2013-07-25 08:22:36 +02:00
|
|
|
cmd_to_write,
|
2013-04-30 03:47:37 +02:00
|
|
|
release_data_needs_write,
|
|
|
|
r_w_mem_cmd_sent,
|
|
|
|
release_data_client_id)
|
|
|
|
}
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
is(s_mem) {
|
2013-01-23 05:09:21 +01:00
|
|
|
when (release_data_needs_write) {
|
2013-05-22 02:19:07 +02:00
|
|
|
doOuterReqWrite(io.master.acquire,
|
|
|
|
io.client.release.data,
|
2013-07-25 08:22:36 +02:00
|
|
|
cmd_to_write,
|
2013-05-22 02:19:07 +02:00
|
|
|
release_data_needs_write,
|
|
|
|
r_w_mem_cmd_sent,
|
2013-04-10 22:46:31 +02:00
|
|
|
release_data_client_id)
|
2013-01-23 05:09:21 +01:00
|
|
|
} . elsewhen(acquire_data_needs_write) {
|
2013-05-22 02:19:07 +02:00
|
|
|
doOuterReqWrite(io.master.acquire,
|
|
|
|
io.client.acquire.data,
|
2013-07-25 08:22:36 +02:00
|
|
|
cmd_to_write,
|
2013-05-22 02:19:07 +02:00
|
|
|
acquire_data_needs_write,
|
|
|
|
a_w_mem_cmd_sent,
|
2013-04-10 22:46:31 +02:00
|
|
|
init_client_id_)
|
2013-01-17 08:57:35 +01:00
|
|
|
} . elsewhen (x_needs_read) {
|
2013-07-25 08:22:36 +02:00
|
|
|
doOuterReqRead(io.master.acquire, cmd_to_read, x_needs_read)
|
2013-01-17 08:57:35 +01:00
|
|
|
} . otherwise {
|
2014-01-21 21:20:55 +01:00
|
|
|
state := Mux(co.requiresDatalessGrant(xact.a_type, UInt(0)), s_ack,
|
|
|
|
Mux(co.requiresAckForGrant(io.client.grant.bits.payload.g_type), s_busy, s_idle))
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
is(s_ack) {
|
2013-03-20 22:10:16 +01:00
|
|
|
io.client.grant.valid := Bool(true)
|
2014-01-21 21:20:55 +01:00
|
|
|
when(io.client.grant.ready) { state := Mux(co.requiresAckForGrant(io.client.grant.bits.payload.g_type), s_busy, s_idle) }
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
is(s_busy) { // Nothing left to do but wait for transaction to complete
|
2013-08-12 19:36:44 +02:00
|
|
|
when (io.client.grant_ack.valid && io.client.grant_ack.bits.payload.master_xact_id === UInt(trackerId)) {
|
2013-01-17 08:57:35 +01:00
|
|
|
state := s_idle
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2013-01-29 01:39:45 +01:00
|
|
|
}
|
|
|
|
|
2013-03-20 22:10:16 +01:00
|
|
|
abstract trait OuterRequestGenerator {
|
2013-08-16 00:27:38 +02:00
|
|
|
val mem_cnt = Reg(init=UInt(0, width = log2Up(REFILL_CYCLES)))
|
2013-08-12 19:36:44 +02:00
|
|
|
val mem_cnt_next = mem_cnt + UInt(1)
|
2013-01-17 08:57:35 +01:00
|
|
|
|
2013-08-12 19:36:44 +02:00
|
|
|
def doOuterReqWrite[T <: HasTileLinkData](master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], client_data: DecoupledIO[LogicalNetworkIO[T]], cmd: Acquire, trigger: Bool, cmd_sent: Bool, desired_client_data_src_id: UInt) {
|
2013-04-10 22:46:31 +02:00
|
|
|
val do_write = client_data.valid && (client_data.bits.header.src === desired_client_data_src_id)
|
2013-07-25 08:22:36 +02:00
|
|
|
master_acq.meta.bits.payload := cmd
|
2013-05-22 02:19:07 +02:00
|
|
|
master_acq.data.bits.payload := client_data.bits.payload
|
|
|
|
when(master_acq.meta.fire()) {
|
2013-01-17 08:57:35 +01:00
|
|
|
cmd_sent := Bool(true)
|
|
|
|
}
|
2013-04-10 22:46:31 +02:00
|
|
|
when (do_write) {
|
2013-05-22 02:19:07 +02:00
|
|
|
master_acq.meta.valid := !cmd_sent
|
|
|
|
when (master_acq.meta.ready || cmd_sent) {
|
|
|
|
master_acq.data.valid := client_data.valid
|
|
|
|
when(master_acq.data.ready) {
|
2013-03-20 22:10:16 +01:00
|
|
|
client_data.ready:= Bool(true)
|
2013-04-10 22:46:31 +02:00
|
|
|
mem_cnt := mem_cnt_next
|
2013-08-12 19:36:44 +02:00
|
|
|
when(mem_cnt === UInt(REFILL_CYCLES-1)) {
|
2013-04-10 22:46:31 +02:00
|
|
|
trigger := Bool(false)
|
2013-01-17 08:57:35 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-07-25 08:22:36 +02:00
|
|
|
def doOuterReqRead(master_acq: PairedDataIO[LogicalNetworkIO[Acquire],LogicalNetworkIO[AcquireData]], cmd: Acquire, trigger: Bool) {
|
2013-05-22 02:19:07 +02:00
|
|
|
master_acq.meta.valid := Bool(true)
|
2013-07-25 08:22:36 +02:00
|
|
|
master_acq.meta.bits.payload := cmd
|
2013-05-22 02:19:07 +02:00
|
|
|
when(master_acq.meta.ready) {
|
2013-01-17 08:57:35 +01:00
|
|
|
trigger := Bool(false)
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|