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Author	SHA1	Message	Date
Henry Styles	e1bfb75188	VC707 Shell : Make DDR and PCIe optional, mixed into Shell with traits. Also add MMCM to provide 65Mhz (and multiples) clock	2017-11-01 14:23:07 -07:00
Henry StylesandGitHub	eaf1c3ed54	Merge pull request #11 from sifive/vc707_use_ip_io_bundles ... VC707 use IP IO bundles	2017-10-24 17:49:31 -07:00
Henry Styles	dc6bb40d1b	VC707 : update contraints file to match PCIe and MIG signal names now claimed directly from the IP	2017-10-23 17:27:36 -07:00
Henry Styles	61b167e8d9	VC707 : use IO bundles directly from the PCIe and MIG devices instead of redeclaring signals	2017-10-23 16:53:59 -07:00
Henry StylesandGitHub	e9019d7570	Merge pull request #5 from sifive/vivado_vsrcs_using_file ... Use a file instead of environment variable to pass VSRCS into Vivado	2017-09-19 14:13:36 -07:00
Henry Styles	97e628639a	Use a file instead of environment variable to pass VSRCS into Vivado	2017-09-19 14:12:23 -07:00
Henry Styles	2bed0c30dc	correct invoke of board specific ip.tcl	2017-09-08 23:20:55 -07:00
Henry StylesandGitHub	07b2ae07d2	Merge pull request #4 from sifive/vc707_2GB ... Support both 4G and 1GB DIMM configuration for VC707	2017-09-08 16:09:18 -07:00
Henry Styles	9f75e6eb59	Support both 4G and 1GB DIMM configuration for VC707 ... Generate IP TCL and MIG projects from the Chisel blackboxes	2017-09-08 15:52:53 -07:00
Henry StylesandGitHub	385ffa7d9a	Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc ... fix PCIe vc707 design contraints : PCIe pins and UART RX sync register	2017-09-07 10:42:32 -07:00
Henry Styles	b7ee0ab0f0	fix PCIe vc707 design contraints : PCIe pins and UART RX sync register	2017-09-07 10:41:12 -07:00