Richard Xia
9593e5eee6
Restructure Tcl script entrypoint.
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vivado.tcl is now the entrypoint for the Vivado Tcl scripts and will
automatically source all the other required scripts.
A command line argument parser was written and replaces the previous system of
using environment variables to pass values into the scripts. The VSRCSVIVADOTCL
environment variable has been replaced with a -F command line option, and the
file format has changed from a Tcl script to a simple newline-delimited list of
files.
2017-10-04 14:15:39 -07:00
Wesley W. Terpstra
4af0552374
diplomacy: update to new API ( #7 )
2017-09-27 16:32:43 -07:00
Megan Wachs
32d4083890
Merge pull request #6 from sifive/signal_bundles
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signal_bundles: Use the new way as .fromPorts is gone
2017-09-25 11:20:44 -07:00
Megan Wachs
bf48e2c7c4
signal_bundles: Use the new way as .fromPorts is gone
2017-09-22 13:31:11 -07:00
Henry Styles
e9019d7570
Merge pull request #5 from sifive/vivado_vsrcs_using_file
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Use a file instead of environment variable to pass VSRCS into Vivado
2017-09-19 14:13:36 -07:00
Henry Styles
97e628639a
Use a file instead of environment variable to pass VSRCS into Vivado
2017-09-19 14:12:23 -07:00
Henry Styles
2bed0c30dc
correct invoke of board specific ip.tcl
2017-09-08 23:20:55 -07:00
Henry Styles
07b2ae07d2
Merge pull request #4 from sifive/vc707_2GB
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Support both 4G and 1GB DIMM configuration for VC707
2017-09-08 16:09:18 -07:00
Henry Styles
9f75e6eb59
Support both 4G and 1GB DIMM configuration for VC707
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Generate IP TCL and MIG projects from the Chisel blackboxes
2017-09-08 15:52:53 -07:00
Megan Wachs
e49f49686d
Merge pull request #1 from sifive/synchronizers
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synchronizers: Use new primitives
2017-09-07 13:33:26 -07:00
Megan Wachs
31650a2d23
Merge remote-tracking branch 'origin/master' into synchronizers
2017-09-07 10:46:03 -07:00
Henry Styles
385ffa7d9a
Merge pull request #3 from sifive/freedomu500vc707devkit_fix_xdc
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fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
2017-09-07 10:42:32 -07:00
Henry Styles
b7ee0ab0f0
fix PCIe vc707 design contraints : PCIe pins and UART RX sync register
2017-09-07 10:41:12 -07:00
Megan Wachs
cab572fab2
synchronizers: decided that ShiftRegInit should be reversed as the others.
2017-09-07 09:54:35 -07:00
Megan Wachs
fd70d118d3
synchronizers: Update constraints to match new hierarchy for synchronizers
2017-09-07 07:50:22 -07:00
Megan Wachs
13671f906d
synchronizers: Use new primitives
2017-09-06 11:00:25 -07:00
Shreesha Srinath
2389e6e957
Fix the package path for xilinx vc707mig
2017-08-18 14:47:03 -07:00
Shreesha Srinath
38afe2957f
Fixing typos in the tcl script
2017-08-18 11:34:35 -07:00
Shreesha Srinath
ae767458af
Pass debug hooks through project-specific makefiles
2017-08-18 11:27:02 -07:00
Shreesha Srinath
c58e79f155
vc707: Updates to the constraints and shell
2017-08-17 18:51:01 -07:00
Shreesha Srinath
ab8cf0775f
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00
