 Wesley W. Terpstra
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4386187016
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vc707: add clock groups dynamically iff they exist
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2018-02-25 14:33:32 -08:00 |
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Wesley W. Terpstra
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b7afc83a34
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xilinx prologue: support tcl for constraints
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2018-02-25 14:32:39 -08:00 |
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 Wesley W. TerpstraandGitHub
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17e13a3a50
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Merge pull request #16 from sifive/chiplink-100
Chiplink 100
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2018-02-08 15:40:16 -08:00 |
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Wesley W. Terpstra
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8519ba8d4e
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vc707: setup 100MHz PLL
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2018-02-08 07:21:45 -08:00 |
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Wesley W. Terpstra
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506d2da883
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vc707: update constraints to match correct mmcm
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2018-02-08 07:21:45 -08:00 |
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Wesley W. Terpstra
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9c38f20333
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vc707 axi: move addresses to line up with ChipLink
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2018-02-08 07:21:44 -08:00 |
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Wesley W. TerpstraandGitHub
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8b0d7ec91a
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TransferSizes: just because a device CAN do more does not mean it should (#15)
Capping TransferSizes at 128 fits nicely in 3 size bits.
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2017-12-10 00:42:11 -08:00 |
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Wesley W. TerpstraandGitHub
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df8e6b8e8c
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xilinxvc707pciex1: use new node-style API and abstract crossing (#13)
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2017-10-28 12:27:24 -07:00 |
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Wesley W. TerpstraandGitHub
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65ac5d4588
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xilinxVC707mig: convert to the island pattern (#12)
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2017-10-26 16:38:52 -07:00 |
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Wesley W. TerpstraandGitHub
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d8e50c7646
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TLToAXI4: remove now unnecessary argument (#10)
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2017-10-12 14:37:21 -07:00 |
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Wesley W. TerpstraandGitHub
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4af0552374
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diplomacy: update to new API (#7)
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2017-09-27 16:32:43 -07:00 |
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