klemens
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2707fa59a4
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Add XilinxML507MIG periphery and connect top level signals
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2018-05-10 00:29:22 +02:00 |
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klemens
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3797385a8c
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Import ml507 mig TL implementation stub
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2018-05-09 23:17:08 +02:00 |
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klemens
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79b53cf2ae
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Add dip switches and clean up top interface
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2018-05-01 00:07:58 +02:00 |
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klemens
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5bcc4e82fd
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Generate separate processor and terminal clocks
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2018-04-30 22:52:02 +02:00 |
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klemens
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9c06418352
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Add terminal/dvi io (unsing the same clock for now)
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2018-04-30 00:41:05 +02:00 |
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klemens
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b2b19cc822
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Add clock and proper reset feedback to ml507
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2018-04-19 01:29:15 +02:00 |
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klemens
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5db71d11c2
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Fix polarity of buttons and dips on the ml507
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2018-04-19 01:28:36 +02:00 |
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klemens
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f4ae1d469f
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Remove unused signals (pcie, mem) from ml507 shell
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2018-04-19 01:27:35 +02:00 |
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klemens
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0b421d5645
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Remove incorrect jtag pin constraints form ml507
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2018-04-19 01:26:15 +02:00 |
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klemens
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8329b232e2
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Hold ml507 in reset while clock not locked
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2018-04-19 01:25:31 +02:00 |
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klemens
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2ff28e6af6
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Add status indication led for the reset button
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2018-04-18 00:26:43 +02:00 |
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klemens
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41362a1cb5
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Remove unused UART signals (rs and cs) from ml507
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2018-04-18 00:26:00 +02:00 |
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klemens
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e9625bf8ee
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Add initial ML507Shell stub based on VC707Shell
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2018-04-12 00:42:46 +02:00 |
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