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fpga-shells
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2707fa59a4ecd32c50d9ef60339f3cc5c3f7bbba
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Klemens Schölhorn
2707fa59a4
Add XilinxML507MIG periphery and connect top level signals
2018-05-10 00:29:22 +02:00
src/main
/scala
Add XilinxML507MIG periphery and connect top level signals
2018-05-10 00:29:22 +02:00
xilinx
prologue: support the absence of an xdc/tcl constraint file
2018-02-25 15:21:03 -08:00
.gitignore
Initial commit for fpga-shells
2017-08-16 11:23:45 -07:00
Description
Freedom FPGA mappings (
https://github.com/sifive/fpga-shells
)
682
KiB
Languages
Scala
89.5%
Tcl
7.8%
Verilog
2%
Makefile
0.7%