riscv/sifive-blocks
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99 Commits

Author SHA1 Message Date
Megan Wachs
79f64de12c peripheral_options: Actually compiles 2017-06-09 13:53:22 -07:00
Megan Wachs
29226701a8 SPIFlash: make it listable 2017-06-08 16:29:01 -07:00
Megan Wachs
c89f163c0d GPIO: Make GPIO peripheral another listable one 2017-06-08 16:25:20 -07:00
Wesley W. Terpstra
0f8722f80c uart: power-on with the right divider for the design (#15) 2017-05-13 23:38:20 -07:00
Wesley W. Terpstra
c4c158963c vc707mig: use an external ibuf 
This makes it possible to also drive a PLL of our own from the crystal.
 2017-05-12 23:07:10 -07:00
Wesley W. Terpstra
0ed21ba465 xilinxvc707pciex1: push to a dedicated clock domain 2017-05-12 23:02:44 -07:00
Wesley W. Terpstra
b3f9607512 xilinx mig: put a buffer infront of the controller (#13) 
This makes placement of the L2 and DDR controller easier.
 2017-05-11 11:50:07 -07:00
Wesley W. Terpstra
178ac84b59 xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12) 2017-05-08 01:08:37 -07:00
Henry Cook
9cb80ac913 Merge pull request #10 from sifive/axi-mmio 
axi4: switch to new pipelined converters
 2017-05-03 11:46:30 -07:00
Albert Ou
75d6a7c6ea spi: Fix off-by-one error in calculating cycles per data frame 
Issue: Configuring the frame length to certain values causes incorrect
operation.

Symptoms: Certain frame lengths result in the master sending one extra
clock pulse.  The slave device may then become desynchronized.

Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
	* Serial mode: 0, 2, 4, 6, 8
	* Dual mode:   0, 1, 3, 5, 7, 8
	* Quad mode:   0, 1, 2, 3, 5, 6, 7, 8
 2017-05-02 12:35:34 -07:00
Albert Ou
eea10f5129 spi: Fix io.port.dq(3) output enable 
Issue: The output enable signal for DQ[3] is not driven properly.

Symptoms: Output data from master to slave is not properly transmitted
in quad mode.  Data received from the slave is unaffected.

Workaround: When interfacing with SPI flash devices, do not use the
"Quad Input/Output Fast Read" command (opcode 0xEB) while in the
Extended SPI protocol.  Do not use the Native Quad SPI protocol.
 2017-05-02 12:07:37 -07:00
Wesley W. Terpstra
a24fa9b444 axi4: switch to new pipelined converters 2017-04-26 13:10:50 -07:00
Henry Styles
6eddf517a3 Merge pull request #9 from sifive/vc707_mig_analog_inout 
Use _chisel3 analog for MIG inout
 2017-04-25 10:18:46 -07:00
Henry Styles
b882d6da93 Use _chisel3 analog for MIG inout 2017-04-25 10:15:00 -07:00
solomatnikov
b1dfcfc0b0 Added stall for read after write (#8) 2017-04-25 09:14:00 -07:00
Megan Wachs
9ba47b76c6 MockAON: Accept the non-debug interrupt as an input to overall reset. 2017-04-07 16:42:32 -07:00
Megan Wachs
70ac4044d1 spi: correct polarity of FIRRTL combo loop detection workaround. 2017-03-31 13:49:34 -07:00
Megan Wachs
1af6ce1c85 Merge remote-tracking branch 'origin/fix-false-comb-loop' into HEAD 2017-03-30 20:01:30 -07:00
Jack Koenig
6a3b5e1a31 "Fix" false combinational loop through SPIArbiter 
Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.
 2017-03-30 19:12:15 -07:00
Yunsup Lee
3c2277447d rename l2FrontendBus as fsb 2017-03-25 19:51:53 -07:00
Yunsup Lee
e2073feef8 rename l2FrontendBus as fsb 2017-03-24 21:38:31 -07:00
Megan Wachs
faeb14dc5a JTAG: make TRSTn optional for all helpers as well to match the IO. 2017-03-24 17:27:55 -07:00
Yunsup Lee
c1872c574b update TLRegisterNode to take Seq of AddressSet 2017-03-21 22:12:37 -07:00
Megan Wachs
c6d7326669 TLSPI: address parameter must now be a sequence. 2017-03-21 17:51:33 -07:00
Megan Wachs
77246eaada Adjust JTAG for rocket-chip changes 2017-03-14 14:52:39 -07:00
Megan Wachs
25356957fe Merge remote-tracking branch 'origin/master' into debug-0.13 2017-03-10 14:09:24 -08:00
Wesley W. Terpstra
46aa6b0ac4 devices: include DTS meta-data 2017-03-02 20:39:30 -08:00
Wesley W. Terpstra
baccd5ada2 devices: create periphery keys for all devices 
Standardize how they are connected to the periphery bus
 2017-03-02 20:39:25 -08:00
Megan Wachs
bf9b81f2bc jtag: The jtag interfaces have moved to a different package. 2017-03-02 14:46:34 -08:00
Megan Wachs
03be9aba67 Use HomogenousBag to handle lists of peripherals 
Previously we had to do weird things to make non-homogenous
lists of items (e.g. PWM Peripherals where ncmp were different from one to
the other) into a vector. But now Chisel supports a Record type,
and we use the HomogenousBag utility to do this more naturally.
This also deletes all the cruft which was introduced to get
around the limitation which doesn't exist anymore.
 2017-02-16 17:52:24 -08:00
Alex Solomatnikov
a915e84a9e Merge remote-tracking branch 'origin/master' into i2c 2017-02-09 18:45:35 -08:00
Alex Solomatnikov
095cb158dd Flipped polarity of output enables to match Guava pins logic 2017-02-09 11:37:40 -08:00
Alex Solomatnikov
72e4b60d81 Made regs 32-bit word aligned to match the rest of the system 2017-02-09 11:36:19 -08:00
Alex Solomatnikov
9ca71c0cf2 Added note: WISHBONE interface replaced by Tilelink2 2017-02-07 16:14:28 -08:00
Alex Solomatnikov
c311b6ec63 Added license 2017-02-07 15:58:04 -08:00
Alex Solomatnikov
5a0d084b38 Renamed i2cDevices to i2c 2017-02-06 10:39:47 -08:00
Wesley W. Terpstra
88e4c8ee20 xilinx mig: track changes in rocket-chip 2017-02-03 18:17:58 -08:00
Alex Solomatnikov
d474b5ceb2 Addressing comments: bool style, comments, removed suggestName 2017-02-03 18:10:03 -08:00
Alex Solomatnikov
3781d1fb1a Bug fixes: passing OC WB test 2017-02-03 16:41:59 -08:00
Wesley W. Terpstra
c010a1557a sifive-blocks: trust diplomacy to get names right 2017-02-01 13:53:54 -08:00
Alex Solomatnikov
2cc1012fa2 Completed Chisel RTL (not tested yet) 2017-01-31 17:20:53 -08:00
Wesley W. Terpstra
535be3e976 spi: work around ucb-bar/chisel3#472 2017-01-31 14:03:14 -08:00
Wesley W. Terpstra
5b6760394d xilinx ip: adjust to new diplomacy API 2017-01-30 11:33:30 -08:00
Alex Solomatnikov
9d2a173b15 Initial (compilable) version of I2C (no actual logic yet) 2017-01-24 14:58:01 -08:00
Wesley W. Terpstra
d61d86e084 xilinx pcie: put buffers before the outputs to the controller 2017-01-20 22:38:27 -08:00
Wesley W. Terpstra
c68e44ec55 mig: track change to Blind port API in rocket 2017-01-19 19:53:03 -08:00
Wesley W. Terpstra
45c491cd69 LazyModule: provide Parameters 
This tracks PR #478 in rocketchip.
 2016-12-07 13:21:20 -08:00
Wesley W. Terpstra
1443834186 xilinx pcie: bytes, not bits 
This bug amazingly compiled correctly and ran correctly!

It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.

The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
 2016-12-06 16:13:12 -08:00
SiFive
7916ef5249 Initial commit. 2016-11-29 04:08:44 -08:00