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riscv/sifive-blocks
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72e4b60d81e5ae1cbc518c9a3bda486a56dfca8c
sifive-blocks/src/main/scala/devices
T
History
Alex Solomatnikov 72e4b60d81 Made regs 32-bit word aligned to match the rest of the system
2017-02-09 11:36:19 -08:00
..
gpio
LazyModule: provide Parameters
2016-12-07 13:21:20 -08:00
i2c
Made regs 32-bit word aligned to match the rest of the system
2017-02-09 11:36:19 -08:00
mockaon
LazyModule: provide Parameters
2016-12-07 13:21:20 -08:00
pwm
LazyModule: provide Parameters
2016-12-07 13:21:20 -08:00
spi
LazyModule: provide Parameters
2016-12-07 13:21:20 -08:00
uart
LazyModule: provide Parameters
2016-12-07 13:21:20 -08:00
xilinxvc707mig
mig: track change to Blind port API in rocket
2017-01-19 19:53:03 -08:00
xilinxvc707pciex1
xilinx pcie: put buffers before the outputs to the controller
2017-01-20 22:38:27 -08:00
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