Andrew Waterman 391a9b9110 Use buses, rather than crossbars, by default in TLInterconnect ...

We should eventually parameterize this, of course.

2016-05-26 16:10:42 -07:00

..

ahb.scala

ahb: backport bridge to chisel2

2016-05-25 13:40:24 -07:00

amoalu.scala

ahb: amoalu does not need so many parameters! (i want to reuse it)

2016-05-24 14:58:27 -07:00

bram.scala

Merge pull request #42 from terpstra/ahb

2016-05-24 17:02:15 -07:00

broadcast.scala

fix BroadcastHub allocation and routing

2016-04-05 16:21:18 -07:00

builder.scala

Add config classes to drive unit testing of L2 TileLink agents.

2016-05-20 16:15:43 -07:00

cache.scala

Ignore way_en in MetadataArray for direct-mapped caches

2016-05-24 15:47:09 -07:00

coherence.scala

fix more Chisel3 deprecations

2016-01-14 14:55:45 -08:00

consts.scala

Let isRead be true for store-conditional

2015-09-25 15:28:02 -07:00

converters.scala

Add generic TileLink width adapter

2016-05-26 15:59:42 -07:00

directory.scala

First pages commit

2015-04-29 13:18:26 -07:00

dma.scala

make sure CSR width is parameterizable

2016-02-02 12:49:58 -08:00

ecc.scala

Chisel3 compatibility: use >>Int instead of >>UInt

2015-08-04 13:15:17 -07:00

htif.scala

Work around zero-width wire limitation in HTIF

2016-05-25 20:39:53 -07:00

interconnect.scala

Use buses, rather than crossbars, by default in TLInterconnect

2016-05-26 16:10:42 -07:00

metadata.scala

Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.

2016-03-10 17:14:34 -08:00

network.scala

Use buses, rather than crossbars, by default in TLInterconnect

2016-05-26 16:10:42 -07:00

package.scala

First pages commit

2015-04-29 13:18:26 -07:00

plic.scala

Improve PLIC QoR

2016-05-10 17:03:56 -07:00

prci.scala

Add trivial version of PRCI block

2016-05-02 17:49:10 -07:00

rom.scala

move NastiROM and HastiRAM into rom.scala and bram.scala

2016-05-06 11:31:22 -07:00

rtc.scala

rtc: fix acquire message type check

2016-05-25 20:37:48 -07:00

scr.scala

print the base address of each SCR as indicated

2016-04-28 16:31:56 +01:00

tilelink.scala

Work around another zero-width wire limitation

2016-05-25 21:42:02 -07:00

uncore.scala

Ensure that a TSHR doesn't see a valid Acquire if that is blocked by a Release,

2016-05-20 16:35:30 -07:00

util.scala

Chisel3 compatibility fix

2016-03-10 17:32:23 -08:00