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  • 61ef560c75
         tilelink: don't pollute TLParamters with AtomicAutomata's implementation (#1111) Wesley W. Terpstra 2017-11-14 17:49:10 -0800
  • 8b79f0394e
         Merge pull request #1105 from freechipsproject/axi4-xbar Wesley W. Terpstra 2017-11-14 16:18:23 -0800
  • 509a48c9c9
         TLToAXI4: block TL early source re-use before it goes to AXI4 (#1110) Wesley W. Terpstra 2017-11-14 16:08:43 -0800
  • e370934c50 AXI4Xbar: reduce number of special cases Wesley W. Terpstra 2017-11-14 13:23:12 -0800
  • 9004ecdf25 unittest: include AXI4Xbar in regression Wesley W. Terpstra 2017-11-13 17:32:30 -0800
  • 5875017956 axi4: add an Xbar Wesley W. Terpstra 2017-11-10 17:29:29 -0800
  • 72c89f7e30 axi4: add a Filter suitable for manipulating test visibility Wesley W. Terpstra 2017-11-14 12:36:28 -0800
  • bfc0ba679a axi4: add a Delayer for unit tests Wesley W. Terpstra 2017-11-14 12:32:32 -0800
  • 1902ba063a Filter: can claim to be out-of-order when you are not Wesley W. Terpstra 2017-11-13 13:15:56 -0800
  • 58a93e2100 AXI4SRAM: handy helper object Wesley W. Terpstra 2017-11-13 13:16:40 -0800
  • 353ddffc11 RAMModel: add a convenience object Wesley W. Terpstra 2017-11-13 13:12:32 -0800
  • 7cfb69e2d5 Queue: silence some warnings Wesley W. Terpstra 2017-11-13 17:32:54 -0800
  • 147fad6387
         Fix AXI4 FIFO ordering for masters with early source reuse (#1108) Wesley W. Terpstra 2017-11-13 20:32:09 -0800
  • 7098ebf439
         rocket: fix itim GetPropertyByHartId (#1109) Henry Cook 2017-11-13 19:25:20 -0800
  • b317735319
         Merge pull request #1106 from freechipsproject/bump-tools Andrew Waterman 2017-11-11 23:36:28 -0800
  • f0a0687589 bump tools for .align 2 fix in riscv-tests Andrew Waterman 2017-11-11 19:13:59 -0800
  • 0cfa801bfc
         coreplex: allow MMIO to be misaligned (#1103) Wesley W. Terpstra 2017-11-10 15:12:28 -0800
  • a061b16ee3
         coreplex: fix typo (#1104) Wesley W. Terpstra 2017-11-10 15:11:56 -0800
  • 35d377d122
         Merge pull request #1100 from freechipsproject/disable-local-amos Andrew Waterman 2017-11-09 21:20:55 -0800
  • 4ebca73d59 Provide option to support AMOs only on I/O, not DTIM/D$ Andrew Waterman 2017-11-09 17:25:10 -0800
  • efdb418559
         Merge pull request #1098 from freechipsproject/frontend Andrew Waterman 2017-11-09 17:44:38 -0800
  • 50ce3f5086
         Merge pull request #1097 from freechipsproject/itim-error Wesley W. Terpstra 2017-11-09 00:17:48 -0800
  • d0c6cbba6b Improve frontend branch prediction Andrew Waterman 2017-11-08 17:23:25 -0800
  • bb9d8264e2 "Correct" ITIM uncorrectable errors Andrew Waterman 2017-11-08 16:47:25 -0800
  • 5c1b34d854 Don't report a TL error if overwriting a whole ITIM word Andrew Waterman 2017-11-08 16:46:57 -0800
  • 9b16d25861 Fix reporting of ITIM error addresses on slave-port accesses Andrew Waterman 2017-11-08 16:46:25 -0800
  • 9441c29d92
         Merge pull request #1096 from freechipsproject/tools Palmer Dabbelt 2017-11-08 17:20:28 -0800
  • b59880fe8e
         Fragmenter: add an option for earlyAck only on PutFulls (#1095) Wesley W. Terpstra 2017-11-08 15:31:19 -0800
  • 8700728a35 Bump riscv-tools, for a new toolchain release Palmer Dabbelt 2017-11-08 14:26:55 -0800
  • 4514adb77c
         Merge pull request #1093 from freechipsproject/local-error-interrupt Andrew Waterman 2017-11-07 14:19:53 -0800
  • d096fd206b
         coreplex: WithStatelessBridge => WithIncoherentTiles (#1092) Henry Cook 2017-11-07 13:47:56 -0800
  • 34f38b0fb1 Don't permit vectoring of high interrupts Andrew Waterman 2017-11-07 01:59:30 -0800
  • 6176b348dc Invalidate TL error bit in D$ once progress is made Andrew Waterman 2017-11-07 00:52:18 -0800
  • d8d4504995 Provide separate masks for local & global BusErrorUnit interrupts Andrew Waterman 2017-11-06 18:01:51 -0800
  • be3a3e0187 Generate local interrupt #128 on bus errors Andrew Waterman 2017-11-06 16:54:21 -0800
  • ac096a89e7 Make BusErrorUnit support 32-bit stores Andrew Waterman 2017-11-06 16:42:29 -0800
  • 6357db0b12 Expose BusErrorUnit non-diplomatically for use as local interrupt Andrew Waterman 2017-11-06 16:39:02 -0800
  • bdda2cb145
         Merge pull request #1089 from freechipsproject/aswaterman-patch-1 Andrew Waterman 2017-11-06 18:03:36 -0800
  • 1f5fb5d643
         Merge pull request #1091 from freechipsproject/atomic-automata-errors Wesley W. Terpstra 2017-11-06 13:58:02 -0800
  • 95d00b13cc Report ITIM slave port errors to BusErrorUnit Andrew Waterman 2017-11-06 12:39:17 -0800
  • c84848afa6 Report ITIM uncorrectable errors over D-channel Andrew Waterman 2017-11-06 12:32:45 -0800
  • 7cc7cd5992 tilelink: AtomicAutomata; add errors to the unit test Wesley W. Terpstra 2017-11-06 12:05:44 -0800
  • 88234ead0d tilelink: generalize ErrorEvaluator to more than just address patterns Wesley W. Terpstra 2017-11-06 11:53:09 -0800
  • 25ea7fa852 tilelink: AtomicAutomata should OR the Get error with the Put error Wesley W. Terpstra 2017-11-06 11:31:23 -0800
  • dcf67b49fa
         BusBypass: only stall A once the last beat is accepted (#1090) Wesley W. Terpstra 2017-11-06 11:13:15 -0800
  • 989eeb78f9 Prevent some unnecessary pipeline replays Andrew Waterman 2017-11-06 11:04:06 -0800
  • c8bc487ab8 Use pseudo-LRU policy in BTB Andrew Waterman 2017-11-03 16:27:04 -0700
  • f859da85ff Disable covers that don't apply to DTIM Andrew Waterman 2017-11-03 15:38:13 -0700
  • d6ede818ee DTIM doesn't accept grants Andrew Waterman 2017-11-03 15:37:48 -0700
  • 7bef935d2a
         Don't emit PTW covers when !usingVM Andrew Waterman 2017-11-03 15:03:27 -0700
  • 7e75d63ba6
         debug: Bump riscv-tools for riscv-tests timeout fix (#1086) Megan Wachs 2017-11-02 14:05:02 -0700
  • 16116991e7
         Fix stateless caching (#1084) Wesley W. Terpstra 2017-11-01 11:05:56 -0700
  • 4ccdbecb63
         Async covers (#1085) Wesley W. Terpstra 2017-11-01 11:03:45 -0700
  • a2b80100e2 Make PseudoLRU policy support non-power-of-2 sizes Andrew Waterman 2017-11-01 01:47:23 -0700
  • 9e77045213
         Merge pull request #1083 from freechipsproject/bump-riscv-tools Richard Xia 2017-10-31 20:55:10 -0700
  • f6ec7b765e Bump riscv-tools. Richard Xia 2017-10-31 17:42:05 -0700
  • 84145959e1
         tilelink: fix error fragmentation from multibeat to multibeat (#1082) Wesley W. Terpstra 2017-10-31 17:34:46 -0700
  • 8ec06151b0
         interrupts: Crossing should use asynchronously reset registers (#1080) Wesley W. Terpstra 2017-10-31 16:29:06 -0700
  • f86489b59e
         JTAG: Use sorted map for stability (#1073) Megan Wachs 2017-10-31 15:33:41 -0700
  • 3db066303b
         Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079) Andrew Waterman 2017-10-31 00:49:56 -0700
  • eaac0f6598
         Merge pull request #1078 from freechipsproject/error-support Wesley W. Terpstra 2017-10-30 22:21:20 -0700
  • 45a904b396 ahb: ignore hrdata on an AHB error Wesley W. Terpstra 2017-10-30 18:07:25 -0700
  • 6318d7d44c ahb: inject fuzzy errors Wesley W. Terpstra 2017-10-30 13:53:23 -0700
  • 2912a76a2b axi4: inject fuzzy errors Wesley W. Terpstra 2017-10-30 13:53:08 -0700
  • e8ed450f13 unit tests: do not use LFSR16 which has a common seed! Wesley W. Terpstra 2017-10-30 15:01:17 -0700
  • ec70e5fb02 apb: inject fuzzy errors Wesley W. Terpstra 2017-10-30 14:00:53 -0700
  • 0280a1f218 tilelink: add the ErrorEvaluator, a test bench error helper Wesley W. Terpstra 2017-10-30 17:05:09 -0700
  • 2d12ddb4ed tilelink: ToAXI4 makes R channel errors sticky Wesley W. Terpstra 2017-10-30 13:35:56 -0700
  • d6f1612812 tilelink: ToAHB should make read errors sticky as well Wesley W. Terpstra 2017-10-30 13:31:43 -0700
  • 4c9d9c6331 tilelink: optimize WidthWidget error circuit to nothing Wesley W. Terpstra 2017-10-30 13:19:58 -0700
  • 0992a459be tilelink: Fragmenter should combine errors Wesley W. Terpstra 2017-10-30 12:22:47 -0700
  • 13d0bf6808 tilelink: Monitor now enforces spec-defined error rules Wesley W. Terpstra 2017-10-30 11:25:59 -0700
  • 5ca04a5c41
         Merge pull request #1077 from freechipsproject/node-style Wesley W. Terpstra 2017-10-28 13:15:28 -0700
  • a954f020a9 diplomacy: use new node style chaining Wesley W. Terpstra 2017-10-27 01:13:19 -0700
  • 6aac658184 diplomacy: convert all helper objects to return nodes Wesley W. Terpstra 2017-10-27 00:45:21 -0700
  • 41705808dd Bus: remove deprecated crossing attach methods Wesley W. Terpstra 2017-10-27 01:32:23 -0700
  • 7cf5d4aa90 diplomacy: define only primary node types Wesley W. Terpstra 2017-10-27 00:26:35 -0700
  • eeb11a2693 coreplex: eliminate dead code Wesley W. Terpstra 2017-10-27 00:25:05 -0700
  • 9f83db998e tile: don't chain too many unneeded TileLink adapters (#1075) Wesley W. Terpstra 2017-10-27 01:12:58 -0700
  • e12bdfdf9b coreplex: attach example external interrupts (#1076) Wesley W. Terpstra 2017-10-27 01:12:42 -0700
  • 13981379c4 CoreplexClockCrossing: add a helper method to decide if a clock is useul (#1074) Wesley W. Terpstra 2017-10-26 23:39:56 -0700
  • 91d8a97f1a Merge pull request #1065 from freechipsproject/better-bus-wrappers Wesley W. Terpstra 2017-10-26 16:48:38 -0700
  • 1d8e539362 coreplex: confirm crossings actually cross the right boundary Wesley W. Terpstra 2017-10-26 15:41:17 -0700
  • 60284082e7 diplomacy: add a hook for injecting code into LazyModule.module scope Wesley W. Terpstra 2017-10-26 15:19:05 -0700
  • a060c37173 diplomacy: expose the API to query a Node for its neighbours Wesley W. Terpstra 2017-10-26 15:08:06 -0700
  • e2d6d4d725 diplomacy: eliminate bindings dead-code Wesley W. Terpstra 2017-10-26 15:02:21 -0700
  • 9e33ccdb05 rocket: clarify intent of boundaryBuffers and move to RocketTile Wesley W. Terpstra 2017-10-26 13:52:34 -0700
  • e76e0f6dce interrupts: add debugstring to nodes to show sync depth in graphml Wesley W. Terpstra 2017-10-26 13:11:47 -0700
  • 2acff8d21f util: delete old long-deprecated crossing code Wesley W. Terpstra 2017-10-26 13:08:09 -0700
  • da7703aee9 crossings: deprecate non-island crossing style Wesley W. Terpstra 2017-10-26 13:03:22 -0700
  • 76df1397e0 crossings: stop using deprecated APIs in tests Wesley W. Terpstra 2017-10-25 17:47:09 -0700
  • 380cc6f03b axi4: now also supports the island pattern Wesley W. Terpstra 2017-10-25 17:46:41 -0700
  • 05d48d1807 TLBuffer: replace TLBufferChain with TLBuffer.chain Wesley W. Terpstra 2017-10-25 16:30:07 -0700
  • ce2b904b19 coreplex: tidy up interrupt crossings Wesley W. Terpstra 2017-10-25 16:13:55 -0700
  • e30906589f coreplex: refactor crossings to use node pattern Wesley W. Terpstra 2017-10-25 14:45:44 -0700
  • 6276ea4291 diplomacy: it possible for NodeHandles to put indirection on their attachment Wesley W. Terpstra 2017-10-25 11:17:17 -0700
  • 8c5e8dd071 coreplex: leverage improved := composition Wesley W. Terpstra 2017-10-25 02:27:01 -0700
  • e894d64bca diplomacy: support := composition Wesley W. Terpstra 2017-10-24 23:34:16 -0700
  • b48ab985d0 coreplex: RocketTileWrapper now HasCrossingHelper Henry Cook 2017-10-23 09:39:01 -0700
  • 9fe35382ea sbus: tile adapters in sbus scope Henry Cook 2017-10-19 20:20:21 -0700