coreplex: RocketTileWrapper now HasCrossingHelper
This commit is contained in:
Henry Cook
Wesley W. Terpstra
parent
9fe35382ea
commit
b48ab985d0
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@ -12,12 +12,6 @@ import freechips.rocketchip.tile.{BaseTile, TileParams, SharedMemoryTLEdge, HasE
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.util._
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/** Enumerates the three types of clock crossing between tiles and system bus */
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sealed trait CoreplexClockCrossing
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case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
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case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
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case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing
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/** BareCoreplex is the root class for creating a coreplex sub-system */
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abstract class BareCoreplex(implicit p: Parameters) extends LazyModule with BindingScope {
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lazy val dts = DTS(bindingTree)
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@ -7,30 +7,34 @@ import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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/** Enumerates the three types of clock crossing between tiles and system bus */
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sealed trait CoreplexClockCrossing
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case class SynchronousCrossing(params: BufferParams = BufferParams.default) extends CoreplexClockCrossing
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case class RationalCrossing(direction: RationalDirection = FastToSlow) extends CoreplexClockCrossing
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case class AsynchronousCrossing(depth: Int, sync: Int = 3) extends CoreplexClockCrossing
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trait HasCrossingHelper extends LazyScope
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{
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this: LazyModule =>
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val crossing: CoreplexClockCrossing
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def cross(x: TLCrossableNode, name: String): TLOutwardNode = {
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def cross(x: TLCrossableNode): TLOutwardNode = {
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val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
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crossing match {
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case SynchronousCrossing(params) => {
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val buffer = this { LazyModule(new TLBuffer(params)) }
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buffer.suggestName(name + "SynchronousBuffer")
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buffer.node := x.node
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buffer.node
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// !!! Why does star resolution fail for tile with no slave devices?
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// this { TLBuffer(params)(x.node) }
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x.node
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}
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case RationalCrossing(direction) => {
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def sourceGen = LazyModule(new TLRationalCrossingSource)
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def sinkGen = LazyModule(new TLRationalCrossingSink(direction))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "RationalSource")
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sink.suggestName(name + "RationalSink")
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source.node := x.node
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sink.node := source.node
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source.node :=? x.node
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sink.node :=? source.node
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sink.node
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}
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case AsynchronousCrossing(depth, sync) => {
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@ -38,27 +42,29 @@ trait HasCrossingHelper extends LazyScope
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def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "AsynchronousSource")
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sink.suggestName(name + "AsynchronousSink")
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source.node := x.node
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sink.node := source.node
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source.node :=? x.node
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sink.node :=? source.node
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sink.node
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}
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}
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}
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def cross(x: IntCrossableNode, name: String, alreadyRegistered: Boolean = false): IntOutwardNode = {
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def cross(
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name: Option[String] = None,
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alreadyRegistered: Boolean = false,
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overrideCrossing: Option[CoreplexClockCrossing] = None)
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(x: IntCrossableNode): IntOutwardNode = {
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val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
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crossing match {
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overrideCrossing.getOrElse(crossing) match {
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case SynchronousCrossing(_) => {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(0))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "SyncSource")
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sink.suggestName(name + "SyncSink")
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source.node := x.node
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sink.node := source.node
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name.map(_ + "SyncSource").foreach(source.suggestName)
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name.map(_ + "SyncSink").foreach(sink.suggestName)
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source.node :=? x.node
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sink.node :=? source.node
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sink.node
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}
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case RationalCrossing(_) => {
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@ -66,10 +72,10 @@ trait HasCrossingHelper extends LazyScope
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def sinkGen = LazyModule(new IntSyncCrossingSink(1))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "SyncSource")
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sink.suggestName(name + "SyncSink")
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source.node := x.node
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sink.node := source.node
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name.map(_ + "SyncSource").foreach(source.suggestName)
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name.map(_ + "SyncSink").foreach(sink.suggestName)
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source.node :=? x.node
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sink.node :=? source.node
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sink.node
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}
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case AsynchronousCrossing(_, sync) => {
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@ -77,10 +83,10 @@ trait HasCrossingHelper extends LazyScope
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def sinkGen = LazyModule(new IntSyncCrossingSink(sync))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "SyncSource")
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sink.suggestName(name + "SyncSink")
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source.node := x.node
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sink.node := source.node
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name.map(_ + "SyncSource").foreach(source.suggestName)
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name.map(_ + "SyncSink").foreach(sink.suggestName)
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source.node :=? x.node
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sink.node :=? source.node
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sink.node
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}
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}
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@ -31,27 +31,26 @@ class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends T
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TLFragmenter(params.beatBytes, maxXferBytes)(outwardBufNode)
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}
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def toSyncSlaves(adapt: TLOutwardNode => TLOutwardNode, name: Option[String]): TLOutwardNode = adapt(outwardBufNode)
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def toAsyncSlaves(sync: Int, adapt: TLOutwardNode => TLOutwardNode, name: Option[String]): TLAsyncOutwardNode = SinkCardinality { implicit p =>
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val source = LazyModule(new TLAsyncCrossingSource(sync))
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name.foreach{ n => source.suggestName(s"${busName}_${n}_TLAsyncCrossingSource")}
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source.node :*= adapt(outwardNode)
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source.node
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}
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def toRationalSlaves(adapt: TLOutwardNode => TLOutwardNode, name: Option[String]): TLRationalOutwardNode = SinkCardinality { implicit p =>
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val source = LazyModule(new TLRationalCrossingSource())
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name.foreach{ n => source.suggestName(s"${busName}_${n}_TLRationalCrossingSource")}
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source.node :*= adapt(outwardNode)
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source.node
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}
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val fromSystemBus: TLInwardNode = {
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val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
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inwardBufNode := atomics.node
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atomics.node
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}
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def toTile(
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adapt: TLOutwardNode => TLOutwardNode,
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to: TLInwardNode,
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name: Option[String] = None) {
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this {
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LazyScope(s"${busName}ToTile${name.getOrElse("")}") {
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SinkCardinality { implicit p =>
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FlipRendering { implicit p =>
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to :*= adapt(outwardNode)
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}
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}
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}
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}
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}
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}
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/** Provides buses that serve as attachment points,
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@ -18,6 +18,7 @@ case class TileMasterPortParams(
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addBuffers: Int = 0,
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blockerCtrlAddr: Option[BigInt] = None,
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cork: Option[Boolean] = None) {
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def adapt(coreplex: HasPeripheryBus)
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(masterNode: TLOutwardNode)
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(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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@ -29,16 +30,15 @@ case class TileMasterPortParams(
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val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
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val tile_master_buffer = LazyModule(new TLBufferChain(addBuffers))
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tile_master_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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val node: Option[TLNode] = TLNodeChain(List(
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Some(tile_master_buffer.node),
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Some(tile_master_fixer.node),
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tile_master_blocker.map(_.node),
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tile_master_cork.map(_.node)).flatten)
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val node: Option[TLNode] = SourceCardinality { implicit p =>
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TLNodeChain(List(
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Some(tile_master_buffer.node),
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Some(tile_master_fixer.node),
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tile_master_blocker.map(_.node),
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tile_master_cork.map(_.node)).flatten)
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}
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tile_master_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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node.foreach { _ :=* masterNode }
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node.getOrElse(masterNode)
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}
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}
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@ -46,6 +46,7 @@ case class TileMasterPortParams(
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case class TileSlavePortParams(
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addBuffers: Int = 0,
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blockerCtrlAddr: Option[BigInt] = None) {
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def adapt(coreplex: HasPeripheryBus)
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(masterNode: TLOutwardNode)
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(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
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@ -55,14 +56,13 @@ case class TileSlavePortParams(
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.map(bp => LazyModule(new BasicBusBlocker(bp)))
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val tile_slave_buffer = LazyModule(new TLBufferChain(addBuffers))
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tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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val node: Option[TLNode] = TLNodeChain(List(
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Some(tile_slave_buffer.node),
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tile_slave_blocker.map(_.node)).flatten)
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val node: Option[TLNode] = SinkCardinality { implicit p =>
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TLNodeChain(List(
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Some(tile_slave_buffer.node),
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tile_slave_blocker.map(_.node)).flatten)
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}
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tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
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node.foreach { _ :*= masterNode }
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node.getOrElse(masterNode)
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}
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}
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@ -70,7 +70,8 @@ case class TileSlavePortParams(
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case class RocketCrossingParams(
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crossingType: CoreplexClockCrossing = SynchronousCrossing(),
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master: TileMasterPortParams = TileMasterPortParams(),
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slave: TileSlavePortParams = TileSlavePortParams()) {
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slave: TileSlavePortParams = TileSlavePortParams(),
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boundaryBuffers: Boolean = false) {
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def knownRatio: Option[Int] = crossingType match {
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case RationalCrossing(_) => Some(2)
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case _ => None
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@ -95,67 +96,72 @@ trait HasRocketTiles extends HasTiles
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case NumRocketTiles => crossingParams
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case _ => throw new Exception("RocketCrossingKey.size must == 1 or == RocketTilesKey.size")
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}
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private val crossingTuples = localIntNodes.zip(tileParams).zip(crossings)
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// Make a wrapper for each tile that will wire it to coreplex devices and crossbars,
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// according to the specified type of clock crossing.
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private val crossingTuples = localIntNodes.zip(tileParams).zip(crossings)
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val tiles: Seq[BaseTile] = crossingTuples.map { case ((lip, tp), crossing) =>
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val pWithExtra = p.alterPartial {
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case TileKey => tp
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case BuildRoCC => tp.rocc
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case SharedMemoryTLEdge => sharedMemoryTLEdge
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case RocketCrossingKey => List(crossing)
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}
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// For legacy reasons, it is convenient to store some state
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// in the global Parameters about the specific tile being built now
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val wrapper = LazyModule(new RocketTileWrapper(
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params = tp,
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crossing = crossing.crossingType,
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boundaryBuffers = crossing.boundaryBuffers
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)(p.alterPartial {
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case TileKey => tp
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case BuildRoCC => tp.rocc
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case SharedMemoryTLEdge => sharedMemoryTLEdge
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case RocketCrossingKey => List(crossing)
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})
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).suggestName(tp.name)
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val wrapper = crossing.crossingType match {
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case SynchronousCrossing(params) => {
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val wrapper = LazyModule(new SyncRocketTile(tp)(pWithExtra))
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sbus.fromSyncTiles(params, crossing.master.adapt(this) _, tp.name) :=* wrapper.masterNode
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FlipRendering { implicit p => wrapper.slaveNode:*= pbus.toSyncSlaves(crossing.slave.adapt(this) _, tp.name) }
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wrapper
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}
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case AsynchronousCrossing(depth, sync) => {
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val wrapper = LazyModule(new AsyncRocketTile(tp)(pWithExtra))
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sbus.fromAsyncTiles(depth, sync, crossing.master.adapt(this) _, tp.name) :=* wrapper.masterNode
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FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toAsyncSlaves(sync, crossing.slave.adapt(this) _, tp.name) }
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wrapper
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}
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case RationalCrossing(direction) => {
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val wrapper = LazyModule(new RationalRocketTile(tp)(pWithExtra))
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sbus.fromRationalTiles(direction, crossing.master.adapt(this) _, tp.name) :=* wrapper.masterNode
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FlipRendering { implicit p => wrapper.slaveNode :*= pbus.toRationalSlaves(crossing.slave.adapt(this) _, tp.name) }
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wrapper
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}
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}
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tp.name.foreach(wrapper.suggestName) // Try to stabilize this name for downstream tools
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// Connect the master ports of the tile to the system bus
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sbus.fromTile(
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adapt = {x: TLOutwardNode => wrapper.cross(x) } andThen
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crossing.master.adapt(this) _,
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from = wrapper.masterNode,
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name = tp.name)
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// Local Interrupts must be synchronized to the core clock
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// before being passed into this module.
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// This allows faster latency for interrupts which are already synchronized.
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// The CLINT and PLIC outputs interrupts that are synchronous to the periphery clock,
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// so may or may not need to be synchronized depending on the Tile's crossing type.
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// Debug interrupt is definitely asynchronous in all cases.
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val asyncIntXbar = LazyModule(new IntXbar)
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asyncIntXbar.suggestName("asyncIntXbar")
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asyncIntXbar.intnode := debug.intnode // debug
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wrapper.asyncIntNode := asyncIntXbar.intnode
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// Connect the slave ports of the tile to the periphery bus
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pbus.toTile(
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adapt = {x: TLOutwardNode => wrapper.cross(x) } compose
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crossing.slave.adapt(this) _,
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to = wrapper.slaveNode,
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name = tp.name)
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val periphIntXbar = LazyModule(new IntXbar)
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periphIntXbar.suggestName("periphIntXbar")
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periphIntXbar.intnode := clint.intnode // msip+mtip
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periphIntXbar.intnode := plic.intnode // meip
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// Handle all the different types of interrupts crossing to or from the tile:
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// 1. Debug interrupt is definitely asynchronous in all cases.
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// 2. The CLINT and PLIC output interrupts are synchronous to the periphery clock,
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// so might need to be synchronized depending on the Tile's crossing type.
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// 3. Local Interrupts are required to already be synchronous to the tile clock.
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// 4. Interrupts coming out of the tile are sent to the PLIC,
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// so might need to be synchronized depending on the Tile's crossing type.
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// NOTE: The order of calls to := matters! They must match how interrupts
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// are decoded from rocket.intNode inside the tile.
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val asyncIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "AsyncIntXbar"))
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asyncIntXbar.intnode := debug.intnode // debug
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wrapper.intXbar.intnode := wrapper.cross( // 1. always crosses
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name = tp.name.map(_ + "AsyncIntXbar"),
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overrideCrossing = Some(AsynchronousCrossing(8,3))
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)(x = asyncIntXbar.intnode)
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val periphIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "PeriphIntXbar"))
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periphIntXbar.intnode := clint.intnode // msip+mtip
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periphIntXbar.intnode := plic.intnode // meip
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if (tp.core.useVM) periphIntXbar.intnode := plic.intnode // seip
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wrapper.periphIntNode := periphIntXbar.intnode
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wrapper.intXbar.intnode := wrapper.cross( // 2. conditionally crosses
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name = tp.name.map(_ + "PeriphIntXbar")
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)(x = periphIntXbar.intnode)
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val coreIntXbar = LazyModule(new IntXbar)
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coreIntXbar.suggestName("coreIntXbar")
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lip.foreach { coreIntXbar.intnode := _ } // lip
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wrapper.coreIntNode := coreIntXbar.intnode
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val coreIntXbar = LazyModule(new IntXbar).suggestName(tp.name.map(_ + "CoreIntXbar"))
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lip.foreach { coreIntXbar.intnode := _ } // lip
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wrapper.intXbar.intnode := coreIntXbar.intnode // 3. never crosses
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wrapper.intOutputNode.foreach { case int =>
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val rocketIntXing = LazyModule(new IntXing(wrapper.outputInterruptXingLatency))
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FlipRendering { implicit p => rocketIntXing.intnode := int }
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plic.intnode := rocketIntXing.intnode
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wrapper.rocket.intOutputNode.foreach { i => // 4. conditionally crosses
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plic.intnode := FlipRendering { implicit p =>
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wrapper.cross(name = tp.name.map(_ + "PeriphIntOutput"))(x = i)
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}
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}
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wrapper
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@ -52,28 +52,17 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
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def fromFrontBus: TLInwardNode = master_splitter.node
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def fromSyncTiles(params: BufferParams, adapt: TLOutwardNode => TLOutwardNode, name: Option[String] = None): TLInwardNode = this {
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val tile_sink = LazyModule(new TLBuffer(params))
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name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLBuffer") }
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master_splitter.node :=* adapt(tile_sink.node)
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tile_sink.node
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}
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def fromRationalTiles(dir: RationalDirection, adapt: TLOutwardNode => TLOutwardNode, name: Option[String] = None): TLRationalInwardNode = this {
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val tile_sink = LazyModule(new TLRationalCrossingSink(direction = dir))
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name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLRationalCrossingSink") }
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master_splitter.node :=* adapt(tile_sink.node)
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tile_sink.node
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}
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||||
def fromAsyncTiles(depth: Int, sync: Int, adapt: TLOutwardNode => TLOutwardNode, name: Option[String] = None): TLAsyncInwardNode = this {
|
||||
val tile_sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
|
||||
name.foreach { n => tile_sink.suggestName(s"${busName}_${n}_TLAsyncCrossingSink") }
|
||||
|
||||
master_splitter.node :=* adapt(tile_sink.node)
|
||||
tile_sink.node
|
||||
def fromTile(
|
||||
adapt: TLOutwardNode => TLOutwardNode,
|
||||
from: TLOutwardNode,
|
||||
name: Option[String] = None) {
|
||||
this {
|
||||
LazyScope(s"${busName}FromTile${name.getOrElse("")}") {
|
||||
SourceCardinality { implicit p =>
|
||||
master_splitter.node :=* adapt(from)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
def fromSyncPorts(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {
|
||||
|
|
|
|||
|
|
@ -25,8 +25,13 @@ abstract class LazyModule()(implicit val p: Parameters)
|
|||
LazyModule.scope = Some(this)
|
||||
parent.foreach(p => p.children = this :: p.children)
|
||||
|
||||
// suggestedName accumulates Some(names), taking the final one. Nones are ignored.
|
||||
private var suggestedName: Option[String] = None
|
||||
def suggestName(x: String) = suggestedName = Some(x)
|
||||
def suggestName(x: String): this.type = suggestName(Some(x))
|
||||
def suggestName(x: Option[String]): this.type = {
|
||||
x.foreach { n => suggestedName = Some(n) }
|
||||
this
|
||||
}
|
||||
|
||||
private lazy val childNames =
|
||||
getClass.getMethods.filter { m =>
|
||||
|
|
|
|||
|
|
@ -25,8 +25,10 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex
|
|||
})
|
||||
)}
|
||||
|
||||
tiles.flatMap(_.dcacheOpt).foreach {
|
||||
sbus.fromSyncTiles(BufferParams.default, TileMasterPortParams().adapt(this) _) :=* _.node
|
||||
tiles.flatMap(_.dcacheOpt).foreach { dc =>
|
||||
sbus.fromTile(
|
||||
adapt = TileMasterPortParams(addBuffers = 1).adapt(this) _,
|
||||
from = dc.node)
|
||||
}
|
||||
|
||||
val pbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), true, false, pbus.beatBytes))
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@ case class RocketTileParams(
|
|||
rocc: Seq[RoCCParams] = Nil,
|
||||
btb: Option[BTBParams] = Some(BTBParams()),
|
||||
dataScratchpadBytes: Int = 0,
|
||||
boundaryBuffers: Boolean = false,
|
||||
trace: Boolean = false,
|
||||
hcfOnUncorrectable: Boolean = false,
|
||||
name: Option[String] = Some("tile"),
|
||||
|
|
@ -188,38 +187,29 @@ class RocketTileWrapperBundle[+L <: RocketTileWrapper](_outer: L) extends BaseTi
|
|||
val halt_and_catch_fire = _outer.rocket.module.io.halt_and_catch_fire.map(_.cloneType)
|
||||
}
|
||||
|
||||
abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters) extends BaseTile(rtp) {
|
||||
val rocket = LazyModule(new RocketTile(rtp))
|
||||
val asyncIntNode : IntInwardNode
|
||||
val periphIntNode : IntInwardNode
|
||||
val coreIntNode : IntInwardNode
|
||||
val intOutputNode = rocket.intOutputNode
|
||||
class RocketTileWrapper(
|
||||
params: RocketTileParams,
|
||||
val crossing: CoreplexClockCrossing,
|
||||
val boundaryBuffers: Boolean = false)
|
||||
(implicit p: Parameters) extends BaseTile(params) with HasCrossingHelper {
|
||||
|
||||
val rocket = LazyModule(new RocketTile(params))
|
||||
|
||||
val masterBuffer = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
|
||||
val masterNode: TLOutwardNode = if (boundaryBuffers) {
|
||||
masterBuffer.node :=* rocket.masterNode
|
||||
masterBuffer.node
|
||||
} else { rocket.masterNode }
|
||||
|
||||
val slaveBuffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
|
||||
val slaveNode: TLInwardNode = DisableMonitors { implicit p => if (boundaryBuffers) {
|
||||
rocket.slaveNode :*= slaveBuffer.node
|
||||
slaveBuffer.node
|
||||
} else { rocket.slaveNode } }
|
||||
|
||||
val intXbar = LazyModule(new IntXbar)
|
||||
|
||||
rocket.intNode := intXbar.intnode
|
||||
|
||||
def optionalMasterBuffer(in: TLOutwardNode): TLOutwardNode = {
|
||||
if (rtp.boundaryBuffers) {
|
||||
val mbuf = LazyModule(new TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1)))
|
||||
mbuf.node :=* in
|
||||
mbuf.node
|
||||
} else {
|
||||
in
|
||||
}
|
||||
}
|
||||
|
||||
def optionalSlaveBuffer(out: TLInwardNode): TLInwardNode = {
|
||||
if (rtp.boundaryBuffers) {
|
||||
val sbuf = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none))
|
||||
DisableMonitors { implicit p => out :*= sbuf.node }
|
||||
sbuf.node
|
||||
} else {
|
||||
out
|
||||
}
|
||||
}
|
||||
|
||||
def outputInterruptXingLatency: Int
|
||||
|
||||
override lazy val module = new BaseTileModule(this, () => new RocketTileWrapperBundle(this)) {
|
||||
// signals that do not change based on crossing type:
|
||||
rocket.module.io.hartid := io.hartid
|
||||
|
|
@ -228,76 +218,3 @@ abstract class RocketTileWrapper(rtp: RocketTileParams)(implicit p: Parameters)
|
|||
io.halt_and_catch_fire.foreach { _ := rocket.module.io.halt_and_catch_fire.get }
|
||||
}
|
||||
}
|
||||
|
||||
class SyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
|
||||
val masterNode = optionalMasterBuffer(rocket.masterNode)
|
||||
val slaveNode = optionalSlaveBuffer(rocket.slaveNode)
|
||||
|
||||
// Fully async interrupts need synchronizers.
|
||||
// Others need no synchronization.
|
||||
val xing = LazyModule(new IntXing(3))
|
||||
val asyncIntNode = xing.intnode
|
||||
|
||||
val periphIntNode = IntIdentityNode()
|
||||
val coreIntNode = IntIdentityNode()
|
||||
|
||||
// order here matters
|
||||
intXbar.intnode := xing.intnode
|
||||
intXbar.intnode := periphIntNode
|
||||
intXbar.intnode := coreIntNode
|
||||
|
||||
def outputInterruptXingLatency = 0
|
||||
}
|
||||
|
||||
class AsyncRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
|
||||
val source = LazyModule(new TLAsyncCrossingSource)
|
||||
source.node :=* rocket.masterNode
|
||||
val masterNode = source.node
|
||||
|
||||
val sink = LazyModule(new TLAsyncCrossingSink)
|
||||
DisableMonitors { implicit p => rocket.slaveNode :*= sink.node }
|
||||
val slaveNode = sink.node
|
||||
|
||||
// Fully async interrupts need synchronizers,
|
||||
// as do those coming from the periphery clock.
|
||||
// Others need no synchronization.
|
||||
val asyncXing = LazyModule(new IntXing(3))
|
||||
val periphXing = LazyModule(new IntXing(3))
|
||||
val asyncIntNode = asyncXing.intnode
|
||||
val periphIntNode = periphXing.intnode
|
||||
val coreIntNode = IntIdentityNode()
|
||||
|
||||
// order here matters
|
||||
intXbar.intnode := asyncXing.intnode
|
||||
intXbar.intnode := periphXing.intnode
|
||||
intXbar.intnode := coreIntNode
|
||||
|
||||
def outputInterruptXingLatency = 3
|
||||
}
|
||||
|
||||
class RationalRocketTile(rtp: RocketTileParams)(implicit p: Parameters) extends RocketTileWrapper(rtp) {
|
||||
val source = LazyModule(new TLRationalCrossingSource)
|
||||
source.node :=* optionalMasterBuffer(rocket.masterNode)
|
||||
val masterNode = source.node
|
||||
|
||||
val sink = LazyModule(new TLRationalCrossingSink(SlowToFast))
|
||||
DisableMonitors { implicit p => optionalSlaveBuffer(rocket.slaveNode) :*= sink.node }
|
||||
val slaveNode = sink.node
|
||||
|
||||
// Fully async interrupts need synchronizers.
|
||||
// Those coming from periphery clock need a
|
||||
// rational synchronizer.
|
||||
// Others need no synchronization.
|
||||
val asyncXing = LazyModule(new IntXing(3))
|
||||
val periphXing = LazyModule(new IntXing(1))
|
||||
val asyncIntNode = asyncXing.intnode
|
||||
val periphIntNode = periphXing.intnode
|
||||
val coreIntNode = IntIdentityNode()
|
||||
|
||||
// order here matters
|
||||
intXbar.intnode := asyncXing.intnode
|
||||
intXbar.intnode := periphXing.intnode
|
||||
intXbar.intnode := coreIntNode
|
||||
|
||||
def outputInterruptXingLatency = 1
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue