riscv/rocket-chip
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  • 38b6c1c820 tilelink2 axi4: RegisterRouter can cut ready dependency Wesley W. Terpstra 2016-10-11 22:24:06 -0700
  • dc26736f32 axi4 tilelink2: include minAlignment and maxAddress in slaves Wesley W. Terpstra 2016-10-11 18:52:25 -0700
  • 538437384a tilelink2 Fragmenter: combine AccessAck errors Wesley W. Terpstra 2016-10-12 16:56:51 -0700
  • 4caa543ad7 tilelink2: Fragmenter should not cut Acquire parameters Wesley W. Terpstra 2016-10-10 11:46:26 -0700
  • 6336f94fa2 tilelink2: only caches can support B requests Wesley W. Terpstra 2016-10-10 11:45:43 -0700
  • 4a975ca380 tilelink2: add a rightOR to go with our leftOR Wesley W. Terpstra 2016-10-11 10:29:31 -0700
  • b2a5d18e37 diplomacy: simplify address range fragmentation Wesley W. Terpstra 2016-10-11 18:28:26 -0700
  • 73e9508c09 Merge pull request #387 from ucb-bar/safer-crossings Wesley W. Terpstra 2016-10-10 14:44:33 -0700
  • b0e33f4a39 tilelink2: use TLArbiter in HintHandler Wesley W. Terpstra 2016-10-07 21:14:03 -0700
  • 683a2e6785 tilelink2: refactor firstlast helper method Wesley W. Terpstra 2016-10-07 20:15:31 -0700
  • a404cd2abf tilelink2: use NodeHandle to restore Crossing.node API Wesley W. Terpstra 2016-10-07 23:38:36 -0700
  • 876609eb0e diplomacy: add NodeHandles to support abstraction Wesley W. Terpstra 2016-10-07 23:35:20 -0700
  • 97af07eb3e tilelink2: clarify use of Isolation Wesley W. Terpstra 2016-10-07 15:01:47 -0700
  • 76388117bb regmapper: detect improper reset sequencing in RegisterCrossing Wesley W. Terpstra 2016-10-07 15:06:37 -0700
  • b5f5ef69c1 regmapper: eliminate race condition in RegisterCrossing bypass Wesley W. Terpstra 2016-10-07 11:45:20 -0700
  • f250426728 tilelink2: blow up if the channels carry data when they should not Wesley W. Terpstra 2016-10-07 14:05:34 -0700
  • 1b09f1360d AsyncQueue: adjust register names to match vals Wesley W. Terpstra 2016-10-08 20:32:08 -0700
  • e7f8a7e9ea AsyncQueue: make it clear that the SyncChain is not Gray specific Wesley W. Terpstra 2016-10-08 20:31:43 -0700
  • 52b8121e68 Apply "async_queue: Give names to all the registers which show up in the queue (#390)" Wesley W. Terpstra 2016-10-08 20:25:19 -0700
  • ffb734ac0e AsyncQueue: disambiguiate the reset_n signal names Wesley W. Terpstra 2016-10-08 11:22:12 -0700
  • 5ee53c61d6 util: clarify an AsyncQueue corner-case Wesley W. Terpstra 2016-10-07 14:21:09 -0700
  • 609fd97a71 util: AsyncQueue detect power-down/reset of non-empty queue Wesley W. Terpstra 2016-10-06 22:41:27 -0700
  • 75bb94017b util: resynchronize AsyncQueue counters when far side resets Wesley W. Terpstra 2016-10-06 22:31:42 -0700
  • 5e2609bdd2 AsyncQueueSource: don't feed reset into normal logic! Wesley W. Terpstra 2016-10-06 20:42:51 -0700
  • 2f6985efd3 crossings: use flip not flip() Wesley W. Terpstra 2016-10-06 20:41:21 -0700
  • 6d6aa3eb13 tilelink2: Isolation must also connect reset_n Wesley W. Terpstra 2016-10-08 22:15:38 -0700
  • cb7b16f1a9 util: exchange resets between AsyncQueue source and sink Wesley W. Terpstra 2016-10-06 20:27:34 -0700
  • 8c7d469a95 Revert "async_queue: Give names to all the registers which show up in the queue (#390)" Wesley W. Terpstra 2016-10-08 20:15:45 -0700
  • b6bc6b7a4d Merge pull request #382 from ucb-bar/axi4 Wesley W. Terpstra 2016-10-10 13:11:12 -0700
  • adf5f1807b tilelink2: ToAXI4 bridge added Wesley W. Terpstra 2016-10-08 21:36:32 -0700
  • e856cbe3a6 axi4: SRAM for testing Wesley W. Terpstra 2016-10-06 14:39:43 -0700
  • abb02aa6f4 axi4: add a RegisterRouter for generic devices Wesley W. Terpstra 2016-10-08 21:39:49 -0700
  • 2f7081aeaf tilelink2: make mask generation reusable Wesley W. Terpstra 2016-10-06 00:36:38 -0700
  • b29d34038e axi4: diplomacy capable AXI4 Wesley W. Terpstra 2016-10-04 17:52:15 -0700
  • dcb9383568 PositionalMultiQueue: work around vcs Lint report Wesley W. Terpstra 2016-10-06 15:34:13 -0700
  • 5d905a5310 PositionalMultiQueue: shared storage FIFO 1-push n-pop Wesley W. Terpstra 2016-10-05 16:26:31 -0700
  • 0af2a5ba02 bump tools Andrew Waterman 2016-10-09 22:15:55 -0700
  • 3a1d8fe482 debug: use a different form of the crossing which doesn't create an AsyncScope (#394) mwachs5 2016-10-09 20:33:18 -0700
  • b5d4b72313 register_crossing: Remove the need for AsyncScope by specifying the master clock and reset. (#393) mwachs5 2016-10-09 15:51:23 -0700
  • 1e69a2dc1c [tilelink2] allow TL monitors to be globally enabled or disabled (#392) Henry Cook 2016-10-09 12:34:10 -0700
  • 53360f4c2c Disable U-mode by default unless S-mode is present Andrew Waterman 2016-10-08 20:49:36 -0700
  • 7f429e8799 Simplify AsyncResetReg Andrew Waterman 2016-10-08 20:36:43 -0700
  • a84a961a39 async_queue: Give names to all the registers which show up in the queue (#390) mwachs5 2016-10-08 17:50:50 -0700
  • 4fd03ffdf1 Fix PopCountAtLeast, un-breaking BTB Andrew Waterman 2016-10-07 21:20:40 -0700
  • 5392219d86 bump riscv-tools Howard Mao 2016-10-07 15:50:43 -0700
  • 4c49fef242 Merge pull request #388 from ucb-bar/cp-safer-crossings mwachs5 2016-10-07 13:45:23 -0700
  • e5ac0f717f tilelink2: split isolation gates by direction Wesley W. Terpstra 2016-10-06 23:06:02 -0700
  • ad618fd55d plic: Fix bit extraction Albert Ou 2016-10-06 18:05:03 -0700
  • b1c777c7a2 Fix PLIC enable bit access for #ints >= tlDataBits Andrew Waterman 2016-10-06 16:21:14 -0700
  • c22438b822 Fix an overly strict D$ assertion Andrew Waterman 2016-10-06 15:52:21 -0700
  • fe641c14a1 tilelink2: Add support for different noise generator in fuzzer (#386) Jacob Chang 2016-10-06 13:20:13 -0700
  • 5980dc160f Don't allow multiple entries for same PC in BTB Andrew Waterman 2016-10-06 09:41:46 -0700
  • 9b8e8a8b9e Add sbt-unidoc plugin; bump sbt-buildinfo version. (#385) Jim Lawson 2016-10-06 10:48:11 -0700
  • eddf1679f5 Use <> instead of := for bi-directional connections Andrew Waterman 2016-10-04 22:28:56 -0700
  • 4f6eb38eeb Enable Verilator parallel builds Andrew Waterman 2016-10-04 22:28:26 -0700
  • 6472d4c245 Print Verilator random seed when +verbose is passed Andrew Waterman 2016-10-04 22:27:28 -0700
  • 67593fdf2d Explicitly zap some S-mode CSRs when not using S-mode Andrew Waterman 2016-10-04 22:23:20 -0700
  • 968851f7e3 Default to configurable priorities Andrew Waterman 2016-10-04 22:22:42 -0700
  • e952f8f222 asyncqueue: Fix typo in the Async Queue (#381) mwachs5 2016-10-04 21:02:06 -0700
  • 064c9ebdc6 Don't report I$ fetch faults on TLB misses! Andrew Waterman 2016-10-04 14:36:58 -0700
  • 516481b68b Improve back-to-back integer multiplication performance Andrew Waterman 2016-10-04 00:04:46 -0700
  • 7b69f1f261 Don't enter D$ flush state machine if grant outstanding Andrew Waterman 2016-10-03 19:55:56 -0700
  • 28beb33943 Make any intervening load/store/fence fail an LR/SC sequence Andrew Waterman 2016-10-03 17:44:31 -0700
  • 23c8b06d4a use $urandom as seed for $random Yunsup Lee 2016-10-03 16:57:23 -0700
  • 62954d543e correctly initialize the active flag Yunsup Lee 2016-10-03 16:38:33 -0700
  • 6ec2e7c5bd tilelink2: Legacy should preserve the access size (#378) Wesley W. Terpstra 2016-10-03 17:25:31 -0700
  • 72e8c6f589 Merge pull request #379 from ucb-bar/axi-prefactor Wesley W. Terpstra 2016-10-03 16:49:37 -0700
  • f05298d9bc tilelink2: move general-purpose code out of tilelink2 package Wesley W. Terpstra 2016-10-03 15:17:36 -0700
  • c85e42a303 tilelink2: Nodes should accept full PortParameters Wesley W. Terpstra 2016-09-28 12:56:03 -0700
  • f2ca2178bf graphML: CTO's like colour Wesley W. Terpstra 2016-10-03 14:07:28 -0700
  • fe0875b084 LazyModule: output final verilog Module name Wesley W. Terpstra 2016-10-02 02:32:07 -0700
  • 0a4ef66894 BaseTop: record top module; more general than GraphML Wesley W. Terpstra 2016-10-02 02:31:30 -0700
  • 5ff3d3d61c correctly initialize with seed Yunsup Lee 2016-10-02 15:49:58 -0700
  • 52c1a053ff tilelink2 RegisterRouter: test fully Decoupled behaviour Wesley W. Terpstra 2016-10-02 00:47:42 -0700
  • 422e6357a4 tilelink2 RegisterCrossing: Queues go from RV to Irrevocable Wesley W. Terpstra 2016-10-02 00:35:57 -0700
  • 02f89fb530 RegMapper: clarify interface is DecoupledIO Wesley W. Terpstra 2016-10-02 00:31:14 -0700
  • 8a268268ad tilelink2 RegField: clarify restrictions on functions Wesley W. Terpstra 2016-10-02 00:00:32 -0700
  • bff0ffa428 tilelink2 RegisterRouter: fix output data glitches Wesley W. Terpstra 2016-10-01 23:55:02 -0700
  • e0188f8aa4 Don't implicitly fence on CSR instructions Andrew Waterman 2016-10-01 19:39:36 -0700
  • b772edcb1b Allow hit-under-MMIO and multiple MMIOs in blocking D$ Andrew Waterman 2016-10-01 19:42:24 -0700
  • 784f0cf0b6 Merge pull request #370 from ucb-bar/move_clint_and_plic mwachs5 2016-10-01 16:18:54 -0700
  • 28eba9b5ac clint/plic: Move the default addresses Megan Wachs 2016-10-01 15:46:55 -0700
  • 9a381e88d1 Suggest sane names for common objects (#369) mwachs5 2016-09-30 16:19:25 -0700
  • 0ebab0976a tilelink2 Isolation: add enable signal (#368) Wesley W. Terpstra 2016-09-30 04:54:40 -0700
  • 891a253bee Merge pull request #367 from ucb-bar/tl2-isolation Wesley W. Terpstra 2016-09-30 02:19:44 -0700
  • d3547a6193 tilelink2: Isolation gate insertion module Wesley W. Terpstra 2016-09-30 01:49:46 -0700
  • 9b0654be52 tilelink2 Crossing: helpful constructor objects Wesley W. Terpstra 2016-09-30 01:48:47 -0700
  • 80f7bb49e3 tilelink2: helper objects operate on OutwardNodes Wesley W. Terpstra 2016-09-30 01:39:35 -0700
  • a1fa0733e5 Merge pull request #366 from ucb-bar/slowio-change Howard Mao 2016-09-29 23:19:53 -0700
  • 4b86802b1a change the configuration interface of SlowIO Howard Mao 2016-09-29 22:16:53 -0700
  • 8730887baa Merge pull request #364 from ucb-bar/tl2-async-nodes Wesley W. Terpstra 2016-09-29 18:18:31 -0700
  • 6d8c965f04 tilelink2 Crossing: cut the crossing between clock domains Wesley W. Terpstra 2016-09-29 17:32:18 -0700
  • 20f42a8762 tilelink2: reuse the halves of the AsyncQueue Wesley W. Terpstra 2016-09-29 17:12:13 -0700
  • 8e4c1e567c tilelink2: add types for a TL clockless interface Wesley W. Terpstra 2016-09-29 15:34:21 -0700
  • 02ce8c2ca4 tilelink2 Nodes: rename RootNode => BaseNode Wesley W. Terpstra 2016-09-29 14:34:52 -0700
  • 754fcf9831 tilelink2: rename BaseNode to SimpleNode Wesley W. Terpstra 2016-09-29 14:33:10 -0700
  • cfdb8ca797 tilelink2 LazyModule: remove obsolete connect method Wesley W. Terpstra 2016-09-29 14:33:54 -0700
  • f2e438833c tilelink2 Nodes: generalize a node into inner and outer halves Wesley W. Terpstra 2016-09-29 14:30:19 -0700
  • ceb9c53c7d Merge pull request #360 from ucb-bar/move-to-util Howard Mao 2016-09-29 15:59:46 -0700
  • 2bdf8c2be7 Merge branch 'master' into move-to-util Andrew Waterman 2016-09-29 14:42:11 -0700