Merge pull request #366 from ucb-bar/slowio-change
Change the configuration interface of SlowIO
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commit
a1fa0733e5
@ -11,20 +11,15 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
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val in_fast = Decoupled(data)
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val in_slow = Decoupled(data).flip
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val clk_slow = Bool(OUTPUT)
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val set_divisor = Valid(Bits(width = 32)).flip
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val divisor = Bits(OUTPUT, 32)
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val divisor = UInt(INPUT, log2Up(divisor_max))
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val hold = UInt(INPUT, log2Up(divisor_max))
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}
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require(divisor_max >= 8 && divisor_max <= 65536 && isPow2(divisor_max))
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val divisor = Reg(init=UInt(divisor_max-1))
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val d_shadow = Reg(init=UInt(divisor_max-1))
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val hold = Reg(init=UInt(divisor_max/4-1))
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val h_shadow = Reg(init=UInt(divisor_max/4-1))
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when (io.set_divisor.valid) {
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d_shadow := io.set_divisor.bits(log2Up(divisor_max)-1, 0)
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h_shadow := io.set_divisor.bits(log2Up(divisor_max)-1+16, 16)
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}
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io.divisor := (hold << 16) | divisor
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val count = Reg{UInt(width = log2Up(divisor_max))}
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val myclock = Reg{Bool()}
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@ -35,8 +30,8 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
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val held = count === (divisor >> 1) + hold
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when (falling) {
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divisor := d_shadow
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hold := h_shadow
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divisor := io.divisor
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hold := io.hold
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count := UInt(0)
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myclock := Bool(false)
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}
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