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regmapper: detect improper reset sequencing in RegisterCrossing

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This commit is contained in:
Wesley W. Terpstra 2016-10-07 15:06:37 -07:00
parent b5f5ef69c1
commit 76388117bb
1 changed files with 21 additions and 0 deletions
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21
src/main/scala/regmapper/RegisterCrossing.scala
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@ -35,6 +35,15 @@ class BusyRegisterCrossing extends Module {
io.master_response_valid := (bypass || io.crossing_request_ready) && busy
}
class RegisterCrossingAssertion extends Module {
val io = new Bundle {
val master_bypass = Bool(INPUT)
val slave_reset = Bool(INPUT)
}
assert (io.master_bypass || !io.slave_reset)
}
// RegField should support connecting to one of these
class RegisterWriteIO[T <: Data](gen: T) extends Bundle {
val request = Decoupled(gen).flip
@ -101,6 +110,12 @@ class RegisterWriteCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
crossing.io.deq.ready := Bool(true)
io.slave_valid := crossing.io.deq.valid
io.slave_register := crossing.io.deq.bits
val assertion = Module(new RegisterCrossingAssertion)
assertion.clock := io.master_clock
assertion.reset := io.master_reset
assertion.io.master_bypass := io.master_bypass
assertion.io.slave_reset := io.slave_reset
}
// RegField should support connecting to one of these
@ -147,6 +162,12 @@ class RegisterReadCrossing[T <: Data](gen: T, sync: Int = 3) extends Module {
crossing.io.enq.valid := Bool(true)
crossing.io.enq.bits := io.slave_register
val assertion = Module(new RegisterCrossingAssertion)
assertion.clock := io.master_clock
assertion.reset := io.master_reset
assertion.io.master_bypass := io.master_bypass
assertion.io.slave_reset := io.slave_reset
}
/** Wrapper to create an