Merge pull request #388 from ucb-bar/cp-safer-crossings
tilelink2: split isolation gates by direction
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commit
4c49fef242
@ -6,7 +6,7 @@ import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import diplomacy._
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class TLIsolation(f: (Bool, UInt) => UInt) extends LazyModule
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class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt) extends LazyModule
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{
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val node = TLAsyncIdentityNode()
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@ -14,34 +14,36 @@ class TLIsolation(f: (Bool, UInt) => UInt) extends LazyModule
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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val iso = Bool(INPUT)
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val iso_out = Bool(INPUT) // Isolate from client to manager
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val iso_in = Bool(INPUT) // Isolate from manager to client
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}
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def ISO[T <: Data](x: T): T = x.fromBits(f(io.iso, x.asUInt))
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def ISOo[T <: Data](x: T): T = x.fromBits(fOut(io.iso_out, x.asUInt))
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def ISOi[T <: Data](x: T): T = x.fromBits(fIn (io.iso_in, x.asUInt))
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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out.a.mem := ISO(in.a.mem)
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out.a.widx := ISO(in.a.widx)
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in.a.ridx := ISO(out.a.ridx)
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out.d.ridx := ISO(in.d.ridx)
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in.d.widx := ISO(out.d.widx)
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in.d.mem := ISO(out.d.mem)
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out.a.mem := ISOo(in .a.mem)
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out.a.widx := ISOo(in .a.widx)
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in .a.ridx := ISOi(out.a.ridx)
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out.d.ridx := ISOo(in .d.ridx)
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in .d.widx := ISOi(out.d.widx)
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in .d.mem := ISOi(out.d.mem)
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if (edgeOut.manager.base.anySupportAcquire && edgeOut.client.base.anySupportProbe) {
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in.b.widx := ISO(out.b.widx)
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in.c.ridx := ISO(out.c.ridx)
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in.e.ridx := ISO(out.e.ridx)
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out.b.ridx := ISO(in.b.ridx)
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out.c.widx := ISO(in.c.widx)
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out.e.widx := ISO(in.e.widx)
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in.b.mem := ISO(out.b.mem)
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out.c.mem := ISO(in.c.mem)
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out.e.mem := ISO(in.e.mem)
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in .b.widx := ISOi(out.b.widx)
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in .c.ridx := ISOi(out.c.ridx)
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in .e.ridx := ISOi(out.e.ridx)
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out.b.ridx := ISOo(in .b.ridx)
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out.c.widx := ISOo(in .c.widx)
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out.e.widx := ISOo(in .e.widx)
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in .b.mem := ISOi(out.b.mem)
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out.c.mem := ISOo(in .c.mem)
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out.e.mem := ISOo(in .e.mem)
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} else {
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in.b.widx := UInt(0)
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in.c.ridx := UInt(0)
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in.e.ridx := UInt(0)
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in .b.widx := UInt(0)
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in .c.ridx := UInt(0)
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in .e.ridx := UInt(0)
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out.b.ridx := UInt(0)
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out.c.widx := UInt(0)
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out.e.widx := UInt(0)
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@ -52,11 +54,13 @@ class TLIsolation(f: (Bool, UInt) => UInt) extends LazyModule
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object TLIsolation
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{
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// applied to the TL source node; y.node := TLIsolation()(x.node)
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// applied to the TL source node; y.node := TLIsolation(fOut, fIn)(x.node)
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// f should insert an isolation gate between the input UInt and its result
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def apply(f: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => Bool) = {
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val iso = LazyModule(new TLIsolation(f))
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// fOut is applied for data flowing from client to manager
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// fIn is applied for data flowing from manager to client
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def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
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val iso = LazyModule(new TLIsolation(fOut, fIn))
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iso.node := x
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(iso.node, () => iso.module.io.iso)
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(iso.node, () => (iso.module.io.iso_out, iso.module.io.iso_in))
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}
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}
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