tilelink2: ToAXI4 bridge added
This commit is contained in:
Wesley W. Terpstra
parent
e856cbe3a6
commit
adf5f1807b
241
src/main/scala/uncore/tilelink2/ToAXI4.scala
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241
src/main/scala/uncore/tilelink2/ToAXI4.scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import diplomacy._
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import util.PositionalMultiQueue
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import uncore.axi4._
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import scala.math.{min, max}
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case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
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dFn = { case (1, _) =>
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// We must erase all client information, because we crush their source Ids
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Seq(AXI4MasterPortParameters(Seq(AXI4MasterParameters(id = IdRange(0, 1 << idBits)))))
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},
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uFn = { case (1, Seq(AXI4SlavePortParameters(slaves, beatBytes))) =>
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val managers = slaves.zipWithIndex.map { case (s, id) =>
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TLManagerParameters(
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address = s.address,
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sinkId = IdRange(id, id+1),
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regionType = s.regionType,
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executable = s.executable,
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nodePath = s.nodePath,
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supportsGet = s.supportsRead,
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supportsPutFull = s.supportsWrite,
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supportsPutPartial = s.supportsWrite)
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// AXI4 is NEVER fifo in TL sense (R+W are independent)
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}
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Seq(TLManagerPortParameters(managers, beatBytes, 0))
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},
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numPO = 1 to 1,
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numPI = 1 to 1)
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class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
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{
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val node = TLToAXI4Node(idBits)
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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val in = io.in(0)
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val out = io.out(0)
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val edgeIn = node.edgesIn(0)
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val edgeOut = node.edgesOut(0)
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val slaves = edgeOut.slave.slaves
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// All pairs of slaves must promise that they will never interleave data
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require (slaves(0).interleavedId.isDefined)
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slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) }
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// We need to keep the following state from A => D: (addr_lo, size, sink, source)
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// All of those fields could potentially require 0 bits (argh. Chisel.)
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// We will pack as many of the lowest bits of state as fit into the AXI ID.
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// Any bits left-over must be put into a bank of Queues.
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// The Queues are indexed by as many of the source bits as fit into the AXI ID.
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// The Queues are deep enough that every source has guaranteed space in its Queue.
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val sourceBits = log2Ceil(edgeIn.client.endSourceId)
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val sinkBits = log2Ceil(edgeIn.manager.endSinkId)
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val sizeBits = log2Ceil(edgeIn.maxLgSize+1)
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val addrBits = log2Ceil(edgeIn.manager.beatBytes)
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val stateBits = addrBits + sizeBits + sinkBits + sourceBits // could be 0
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val a_address = edgeIn.address(in.a.bits)
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val a_addr_lo = edgeIn.addr_lo(a_address)
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val a_source = in.a.bits.source
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val a_sink = edgeIn.manager.findIdStartFast(a_address)
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val a_size = edgeIn.size(in.a.bits)
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val a_isPut = edgeIn.hasData(in.a.bits)
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val a_counter = RegInit(UInt(0, width = log2Up(edgeIn.maxTransfer)))
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val a_beats1 = edgeIn.numBeats1(in.a.bits)
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val a_first = a_counter === UInt(0)
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val a_last = a_counter === UInt(1) || a_beats1 === UInt(0)
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when (in.a.fire()) {
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a_counter := Mux(a_first, a_beats1, a_counter - UInt(1))
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}
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// Make sure the fields are within the bounds we assumed
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assert (a_source < UInt(1 << sourceBits))
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assert (a_sink < UInt(1 << sinkBits))
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assert (a_size < UInt(1 << sizeBits))
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assert (a_addr_lo < UInt(1 << addrBits))
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// Carefully pack/unpack fields into the state we send
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val baseEnd = 0
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val (sourceEnd, sourceOff) = (sourceBits + baseEnd, baseEnd)
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val (sinkEnd, sinkOff) = (sinkBits + sourceEnd, sourceEnd)
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val (sizeEnd, sizeOff) = (sizeBits + sinkEnd, sinkEnd)
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val (addrEnd, addrOff) = (addrBits + sizeEnd, sizeEnd)
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require (addrEnd == stateBits)
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val a_state = (a_source << sourceOff) | (a_sink << sinkOff) |
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(a_size << sizeOff) | (a_addr_lo << addrOff)
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val a_id = if (idBits == 0) UInt(0) else a_state
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val r_state = Wire(UInt(width = stateBits))
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val r_source = if (sourceBits > 0) r_state(sourceEnd-1, sourceOff) else UInt(0)
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val r_sink = if (sinkBits > 0) r_state(sinkEnd -1, sinkOff) else UInt(0)
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val r_size = if (sizeBits > 0) r_state(sizeEnd -1, sizeOff) else UInt(0)
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val r_addr_lo = if (addrBits > 0) r_state(addrEnd -1, addrOff) else UInt(0)
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val b_state = Wire(UInt(width = stateBits))
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val b_source = if (sourceBits > 0) b_state(sourceEnd-1, sourceOff) else UInt(0)
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val b_sink = if (sinkBits > 0) b_state(sinkEnd -1, sinkOff) else UInt(0)
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val b_size = if (sizeBits > 0) b_state(sizeEnd -1, sizeOff) else UInt(0)
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val b_addr_lo = if (addrBits > 0) b_state(addrEnd -1, addrOff) else UInt(0)
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val r_last = out.r.bits.last
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val r_id = out.r.bits.id
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val b_id = out.b.bits.id
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if (stateBits <= idBits) { // No need for any state tracking
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r_state := r_id
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b_state := b_id
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} else {
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val bankIndexBits = min(sourceBits, idBits)
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val posBits = max(0, sourceBits - idBits)
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val implicitBits = max(idBits, sourceBits)
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val bankBits = stateBits - implicitBits
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val numBanks = min(1 << bankIndexBits, edgeIn.client.endSourceId)
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def bankEntries(i: Int) = (edgeIn.client.endSourceId+numBanks-i-1) / numBanks
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val banks = Seq.tabulate(numBanks) { i =>
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// We know there can only be as many outstanding requests as TL sources
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// However, AXI read and write queues are not mutually FIFO.
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// Therefore, we want to pop them individually, but share the storage.
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PositionalMultiQueue(UInt(width=max(1,bankBits)), positions=bankEntries(i), ways=2, combinational=combinational)
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}
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val a_bankPosition = if (posBits == 0) UInt(0) else a_source(sourceBits-1, idBits)
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val a_bankIndex = if (bankIndexBits == 0) UInt(0) else a_source(bankIndexBits-1, 0)
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val r_bankIndex = if (bankIndexBits == 0) UInt(0) else r_id(bankIndexBits-1, 0)
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val b_bankIndex = if (bankIndexBits == 0) UInt(0) else b_id(bankIndexBits-1, 0)
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val a_bankSelect = UIntToOH(a_bankIndex, numBanks)
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val r_bankSelect = UIntToOH(r_bankIndex, numBanks)
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val b_bankSelect = UIntToOH(b_bankIndex, numBanks)
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banks.zipWithIndex.foreach { case (q, i) =>
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// Push a_state into the banks
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q.io.enq.valid := in.a.fire() && a_last && a_bankSelect(i)
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q.io.enq.bits.pos := a_bankPosition
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q.io.enq.bits.data := a_state >> implicitBits
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q.io.enq.bits.way := Mux(a_isPut, UInt(0), UInt(1))
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// Pop the bank's ways
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q.io.deq(0).ready := out.b.fire() && b_bankSelect(i)
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q.io.deq(1).ready := out.r.fire() && r_bankSelect(i) && r_last
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// The FIFOs must be valid when we're ready to pop them...
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assert (q.io.deq(0).valid || !q.io.deq(0).ready)
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assert (q.io.deq(1).valid || !q.io.deq(1).ready)
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}
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val b_bankData = Vec(banks.map(_.io.deq(0).bits.data))(b_bankIndex)
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val b_bankPos = Vec(banks.map(_.io.deq(0).bits.pos ))(b_bankIndex)
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val r_bankData = Vec(banks.map(_.io.deq(1).bits.data))(r_bankIndex)
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val r_bankPos = Vec(banks.map(_.io.deq(1).bits.pos ))(r_bankIndex)
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def optCat(x: (Boolean, UInt)*) = { Cat(x.toList.filter(_._1).map(_._2)) }
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b_state := optCat((bankBits > 0, b_bankData), (posBits > 0, b_bankPos), (idBits > 0, b_id))
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r_state := optCat((bankBits > 0, r_bankData), (posBits > 0, r_bankPos), (idBits > 0, r_id))
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}
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// We need these Queues because AXI4 queues are irrevocable
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val depth = if (combinational) 1 else 2
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val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params)))
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val out_w = Wire(out.w)
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out.w <> Queue.irrevocable(out_w, entries=depth, pipe=combinational, flow=combinational)
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val queue_arw = Queue.irrevocable(out_arw, entries=depth, pipe=combinational, flow=combinational)
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// Fan out the ARW channel to AR and AW
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out.ar.bits := queue_arw.bits
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out.aw.bits := queue_arw.bits
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out.ar.valid := queue_arw.valid && !queue_arw.bits.wen
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out.aw.valid := queue_arw.valid && queue_arw.bits.wen
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queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready)
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val beatBytes = edgeIn.manager.beatBytes
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val maxSize = UInt(log2Ceil(beatBytes))
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val doneAW = RegInit(Bool(false))
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when (in.a.fire()) { doneAW := !a_last }
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val arw = out_arw.bits
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arw.wen := a_isPut
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arw.id := a_id // truncated
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arw.addr := a_address
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arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes)
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arw.size := Mux(a_size >= maxSize, maxSize, a_size)
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arw.burst := AXI4Parameters.BURST_INCR
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arw.lock := UInt(0) // not exclusive (LR/SC unsupported b/c no forward progress guarantee)
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arw.cache := UInt(0) // do not allow AXI to modify our transactions
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arw.prot := AXI4Parameters.PROT_PRIVILEDGED
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arw.qos := UInt(0) // no QoS
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in.a.ready := Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready)
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out_arw.valid := in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, Bool(true))
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out_w.valid := in.a.valid && a_isPut && (doneAW || out_arw.ready)
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out_w.bits.data := in.a.bits.data
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out_w.bits.strb := in.a.bits.mask
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out_w.bits.last := a_last
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// R and B => D arbitration
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val r_holds_d = RegInit(Bool(false))
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when (out.r.fire()) { r_holds_d := !out.r.bits.last }
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// Give R higher priority than B
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val r_wins = out.r.valid || r_holds_d
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out.r.ready := in.d.ready
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out.b.ready := in.d.ready && !r_wins
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in.d.valid := Mux(r_wins, out.r.valid, out.b.valid)
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val r_error = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
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val b_error = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY
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val r_d = edgeIn.AccessAck(r_addr_lo, r_sink, r_source, r_size, UInt(0), r_error)
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val b_d = edgeIn.AccessAck(b_addr_lo, b_sink, b_source, b_size, b_error)
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in.d.bits := Mux(r_wins, r_d, b_d)
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in.d.bits.data := out.r.bits.data // avoid a costly Mux
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// Tie off unused channels
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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}
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}
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object TLToAXI4
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{
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// applied to the TL source node; y.node := TLToAXI4(idBits)(x.node)
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def apply(idBits: Int, combinational: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
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val axi4 = LazyModule(new TLToAXI4(idBits, combinational))
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axi4.node := x
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axi4.node
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}
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}
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