riscv/rocket-chip
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  • 09afbbafdb ahb: weaken RegisterRouter assertion Wesley W. Terpstra 2016-12-08 10:45:45 -08:00
  • 588b944ed4 ahb: implement and test address decoding Wesley W. Terpstra 2016-12-08 00:06:32 -08:00
  • 5d1064fcb1 ahb: include a unit test Wesley W. Terpstra 2016-12-07 20:56:28 -08:00
  • 51dfb9cb06 ahb: TileLink master Wesley W. Terpstra 2016-12-07 20:47:11 -08:00
  • 01b0f6a52b ahb: new diplomacy-based AHB bus definition Wesley W. Terpstra 2016-12-07 17:27:58 -08:00
  • 54cc071a64 Fix Fragmenter to ensure logical operations must be sent out atomically. Jacob Chang 2016-12-07 16:22:05 -08:00
  • 1bd8a2e239 Merge pull request #478 from ucb-bar/parameterize-diplomatic-connections Wesley W. Terpstra 2016-12-07 15:03:53 -08:00
  • c2eedbfe23 tilelink2 Monitor: use Parameters instead of global variables Wesley W. Terpstra 2016-12-01 19:04:31 -08:00
  • 020fbe8be9 diplomacy: make config.Parameters available in bundle connect() Wesley W. Terpstra 2016-12-01 17:46:52 -08:00
  • 915697cb09 Fix FEQ flag generation (#479) Andrew Waterman 2016-12-06 11:54:29 -08:00
  • fbfa15efea TLBroadcast: support non-FIFO devices (#482) Wesley W. Terpstra 2016-12-05 22:10:37 -08:00
  • 3c9718ec8f clint: undefined registers must be zero (#480) Wesley W. Terpstra 2016-12-05 17:11:53 -08:00
  • f3d0692619 Make a directory for the config package (#464) Henry Cook 2016-12-05 10:42:16 -08:00
  • d0a0c887dc [tracegen] decrease default address bag size (#462) Henry Cook 2016-12-04 22:46:55 -08:00
  • 36fe024671 CacheName no longer needed in RoCCInterface Schuyler Eldridge 2016-11-29 21:49:40 -05:00
  • 624db2034b Make instantiated RoCC use dcacheParams Schuyler Eldridge 2016-11-29 19:34:26 -05:00
  • 9fb7934a37 WIP PR to figure out why travis is failing (#471) Henry Cook 2016-12-04 13:10:13 -08:00
  • 9ac78a0d37 Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests Jacob Chang 2016-12-02 14:21:36 -08:00
  • e8d3b647f2 Removed val from case class for Parameters Jacob Chang 2016-12-01 18:35:43 -08:00
  • 053f81d7c6 minor Changes needed to support formal tests Jacob Chang 2016-12-01 14:55:25 -08:00
  • aa39b3d09d Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests Jacob Chang 2016-12-01 18:37:13 -08:00
  • be23189f77 Removed val from case class for Parameters Jacob Chang 2016-12-01 18:35:43 -08:00
  • 6d402ff1af minor Changes needed to support formal tests Jacob Chang 2016-12-01 14:55:25 -08:00
  • 60889df576 Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests Jacob Chang 2016-12-01 15:17:30 -08:00
  • cff2612cdb minor Changes needed to support formal tests Jacob Chang 2016-12-01 14:55:25 -08:00
  • a49b6d6569 Merge branch 'formal_tests' of github.com:ucb-bar/rocket-chip into formal_tests Jacob Chang 2016-12-01 15:01:52 -08:00
  • 5e9496fd14 minor Changes needed to support formal tests Jacob Chang 2016-12-01 14:55:25 -08:00
  • 75512e9aa0 minor Changes needed to support formal tests Jacob Chang 2016-12-01 14:55:25 -08:00
  • 4234cff074 Merge pull request #444 from ucb-bar/bump-submodules Henry Cook 2016-11-29 00:13:00 -08:00
  • 131659cc2a Merge branch 'master' into bump-submodules Henry Cook 2016-11-28 16:20:42 -08:00
  • d07e30ba97 Update README.md heinzbeinz 2016-11-23 13:47:38 +01:00
  • a8ee7e0678 Update README Henry Cook 2016-11-28 16:10:50 -08:00
  • 18d100c2b5 Merge pull request #461 from ucb-bar/sifive-copyright Yunsup Lee 2016-11-28 15:25:33 -08:00
  • 86065e5fb8 Merge remote-tracking branch 'origin/master' into bump-submodules Henry Cook 2016-11-28 13:49:59 -08:00
  • b7963eca4e copyright: ran scripts/modify-copyright Wesley W. Terpstra 2016-11-27 16:16:37 -08:00
  • d4708694ea scripts/authors: Matthew Naylor's submissions were under Berkeley terms Wesley W. Terpstra 2016-11-27 16:13:55 -08:00
  • e2ec1d00ad copyright: normalize /// to // in comments Wesley W. Terpstra 2016-11-27 16:11:41 -08:00
  • a0e10aec05 uncore: removed obsolete Builder file Wesley W. Terpstra 2016-11-27 19:18:35 -08:00
  • 8510d9e697 scripts: two scripts to determine copyright holder of files Wesley W. Terpstra 2016-11-27 15:36:02 -08:00
  • 4146f6a792 TLB: do not access illegal addresses (#460) Wesley W. Terpstra 2016-11-26 15:11:42 -08:00
  • 97a853a995 Merge pull request #459 from ucb-bar/bump-chisel-for-firrtl-jar-gitignore Richard Xia 2016-11-26 13:55:53 -08:00
  • 4e3682f889 Bump chisel3 by just one commit to pull in gitignore for firrtl.jar. Richard Xia 2016-11-26 12:24:10 -08:00
  • a17753983a coreplex: allow legacy devices to override the config string (#458) Wesley W. Terpstra 2016-11-25 19:38:24 -08:00
  • 9433da8458 Merge pull request #457 from ucb-bar/jtag-depth-1 Wesley W. Terpstra 2016-11-25 18:41:39 -08:00
  • 233280e7d2 AsyncBundle: save a wasted bit when depth=1 Wesley W. Terpstra 2016-11-25 18:11:01 -08:00
  • d755edffcc DebugTransport: use ToAsyncDebugBus for correct depth Wesley W. Terpstra 2016-11-25 18:10:28 -08:00
  • 2b80386a9e rocketchip: TileInterrupts needs a TLCacheEdge (#456) Wesley W. Terpstra 2016-11-25 17:02:29 -08:00
  • 1e0aca7358 dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455) Wesley W. Terpstra 2016-11-25 15:26:22 -08:00
  • f19d504c88 Use % in makefrag-verilog to prevent double firrtl execution (#452) Colin Schmidt 2016-11-25 01:50:01 -08:00
  • 0baa1c9a45 coreplex: CacheBlockOffsetBits was wrong! Wesley W. Terpstra 2016-11-24 15:50:49 -08:00
  • 549e006988 Merge pull request #451 from ucb-bar/more-configs Yunsup Lee 2016-11-24 09:44:52 -08:00
  • 6aeadc4551 regression: disable ComparatorL2Config for now Wesley W. Terpstra 2016-11-23 20:53:36 -08:00
  • a670f63c81 periphery: a handy trait to turn-off ExtMem Wesley W. Terpstra 2016-11-23 18:53:22 -08:00
  • 30e890b480 diplomacy: include InternalNodes for AXI4 and TL Wesley W. Terpstra 2016-11-23 18:53:03 -08:00
  • 9f1c668c4f config: when modifying Parameters, subordinate lookups use top Wesley W. Terpstra 2016-11-23 18:06:33 -08:00
  • 566cc9e60b rocketchip: RTCPeriod config Wesley W. Terpstra 2016-11-23 16:04:54 -08:00
  • e87f54d4f7 rocketchip: traits for adding external TL2 ports Wesley W. Terpstra 2016-11-23 15:37:08 -08:00
  • 4b9dc78951 rocketchip: add a parameter-controlled debug port Wesley W. Terpstra 2016-11-23 15:35:53 -08:00
  • 76fa62a928 Merge pull request #449 from ucb-bar/post-refactor-cleanup Henry Cook 2016-11-23 13:35:23 -08:00
  • 837d207064 [travis] split up groundtest into two suites Henry Cook 2016-11-23 12:18:18 -08:00
  • 38c5af5bad [rocket] cleanup mshr logic Henry Cook 2016-11-23 12:02:23 -08:00
  • dae6772624 factor out common cache subcomponents into uncore.util Henry Cook 2016-11-22 11:50:41 -08:00
  • 16d0f522b0 [tracegen] filter seed report Henry Cook 2016-11-22 11:05:30 -08:00
  • c65c255815 [coreplex] TileId moved to groundtest Henry Cook 2016-11-22 10:53:44 -08:00
  • cf8ecbd53b travis: balance regression tasks a bit more fairly Wesley W. Terpstra 2016-11-23 01:01:16 -08:00
  • e8e95d4bcf regression: remove cde submodule update Wesley W. Terpstra 2016-11-22 01:53:35 -08:00
  • a93d34742a rocketchip: bump all submodules (and remove cde) Wesley W. Terpstra 2016-11-21 22:55:48 -08:00
  • 612f96b2af Merge pull request #447 from ucb-bar/axi4-master Wesley W. Terpstra 2016-11-23 10:23:43 -08:00
  • 1d3cad3671 tilelink2 SourceShrinker: handle degenerate cases for free Wesley W. Terpstra 2016-11-22 22:01:43 -08:00
  • 1e7d597fd3 rocketchip: don't waste too many sources on the AXI master port Wesley W. Terpstra 2016-11-22 21:48:41 -08:00
  • c0b27999ea tilelink2 SourceShrinker: a concurrency reducing adapter Wesley W. Terpstra 2016-11-22 21:20:26 -08:00
  • 0097274ea3 Broadcast: single-cycle response is possible Wesley W. Terpstra 2016-11-22 20:45:40 -08:00
  • 437be0f36a PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool)) Wesley W. Terpstra 2016-11-22 20:39:38 -08:00
  • f9de7173cc PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...)) Wesley W. Terpstra 2016-11-22 18:46:11 -08:00
  • d9a203b0f0 PositionalMultiQueue: convert 'next' to a single write port Wesley W. Terpstra 2016-11-22 18:38:55 -08:00
  • 13190a5de0 rocketchip: re-add AXI4 interface Wesley W. Terpstra 2016-11-22 16:58:24 -08:00
  • c230580157 coreplex: rename RocketPlex => RocketTiles Wesley W. Terpstra 2016-11-22 15:49:06 -08:00
  • bbabcf67ff coreplex: width adapter should happen as part of coherence manager Wesley W. Terpstra 2016-11-22 15:12:45 -08:00
  • a140b07009 rocketchip: cut coreplex from rocketchip Wesley W. Terpstra 2016-11-22 15:01:45 -08:00
  • c80ee06472 rocketchip: configString is a lazy property of outer Wesley W. Terpstra 2016-11-22 14:58:03 -08:00
  • 5f3fb64ef0 Per ABI, only x1 and x5 should be treated as function returns Andrew Waterman 2016-11-20 16:35:27 -08:00
  • 42b40130e2 Merge pull request #443 from ucb-bar/tl2-tlb Yunsup Lee 2016-11-21 22:00:30 -08:00
  • 3d644b943c coreplex: configString is a property of the RISCVPlatform Wesley W. Terpstra 2016-11-21 16:11:16 -08:00
  • e8be365b5d rocketchip: remove GlobalAddrMap completely Wesley W. Terpstra 2016-11-21 12:45:00 -08:00
  • 5fe107bb07 rocket: pass scratchpad address to block dcache Wesley W. Terpstra 2016-11-21 12:19:33 -08:00
  • c18bc07bbc TLB: determine RWX from TL2 properties directly Wesley W. Terpstra 2016-11-21 11:48:10 -08:00
  • 3d1a7bd6d3 travis: build verilator and toolchain as part of install Wesley W. Terpstra 2016-11-21 17:37:14 -08:00
  • ea3ec89676 travis: split RocketSuite into three smaller tests suites Wesley W. Terpstra 2016-11-21 15:12:05 -08:00
  • 1577deb324 travis: delete oldest caches; not newest Wesley W. Terpstra 2016-11-21 16:51:52 -08:00
  • 94cc1efadc Merge pull request #440 from ucb-bar/tl2-tile Henry Cook 2016-11-20 20:44:59 -08:00
  • 28c6be90ab [rocket] require refillcycesperbeat == 1 and remove flowthroughserializer Henry Cook 2016-11-20 19:36:51 -08:00
  • ff9b5bf8fc [rocket] nbdcache release bugfix Henry Cook 2016-11-20 19:07:06 -08:00
  • e68795421a remove L2 regressions for now Henry Cook 2016-11-19 20:11:20 -08:00
  • 3f47d5b5eb [rocket] re-enable working NBDcache (passes Tracegen) Henry Cook 2016-11-19 19:19:16 -08:00
  • c31b41a7ac [tl2] add grant finisher comment Henry Cook 2016-11-19 19:16:43 -08:00
  • 9dd12545d0 [Rocket] Send correct type for iomshr reqs Colin Schmidt 2016-11-18 17:18:42 -08:00
  • 32a1c27441 rocket: disable nbdcache until it's fully ported Wesley W. Terpstra 2016-11-18 19:55:24 -08:00
  • 452bb2fc80 dcache fix TinyConfig Wesley W. Terpstra 2016-11-18 19:50:34 -08:00
  • d1328a6b6f rocketchip: remove most uses of GlobalAddrMap Wesley W. Terpstra 2016-11-18 19:38:02 -08:00
  • 2976fd84e4 [rocket] resolve cde/config conflicts Henry Cook 2016-11-18 19:11:34 -08:00