Merge pull request #478 from ucb-bar/parameterize-diplomatic-connections
Parameterize diplomatic connections
This commit is contained in:
commit
1bd8a2e239
@ -31,7 +31,8 @@ case object BroadcastConfig extends Field[BroadcastConfig]
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case class BankedL2Config(
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nMemoryChannels: Int = 1,
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nBanksPerChannel: Int = 1,
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coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case p =>
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coherenceManager: Parameters => (TLInwardNode, TLOutwardNode) = { case q =>
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implicit val p = q
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val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
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val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
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(bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node))
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@ -54,9 +55,10 @@ trait HasCoreplexParameters {
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case class CoreplexParameters(implicit val p: Parameters) extends HasCoreplexParameters
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abstract class BareCoreplex(implicit val p: Parameters) extends LazyModule
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abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends Bundle {
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abstract class BareCoreplex(implicit p: Parameters) extends LazyModule
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abstract class BareCoreplexBundle[+L <: BareCoreplex](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareCoreplexModule[+L <: BareCoreplex, +B <: BareCoreplexBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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val outer = _outer
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@ -96,7 +98,6 @@ trait CoreplexNetwork extends HasCoreplexParameters {
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trait CoreplexNetworkBundle extends HasCoreplexParameters {
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val outer: CoreplexNetwork
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implicit val p = outer.p
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val mmio = outer.mmio.bundleOut
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val interrupts = outer.mmioInt.bundleIn
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}
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@ -105,8 +106,6 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
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val outer: CoreplexNetwork
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val io: CoreplexNetworkBundle
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implicit val p = outer.p
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println("\nGenerated Address Map")
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for (manager <- outer.l1tol2.node.edgesIn(0).manager.managers) {
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val prot = (if (manager.supportsGet) "R" else "") +
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@ -207,7 +207,7 @@ class WithStatelessBridge extends Config(
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(pname,site,here,up) => pname match {
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/* !!! FIXME
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case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (_, _) =>
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val pass = LazyModule(new TLBuffer(0))
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val pass = LazyModule(new TLBuffer(0)(site))
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(pass.node, pass.node)
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})
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*/
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@ -3,9 +3,10 @@
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package diplomacy
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import Chisel._
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import config._
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import chisel3.internal.sourceinfo.{SourceInfo, SourceLine, UnlocatableSourceInfo}
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abstract class LazyModule
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abstract class LazyModule()(implicit val p: Parameters)
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{
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protected[diplomacy] var bindings = List[() => Unit]()
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protected[diplomacy] var children = List[LazyModule]()
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@ -112,4 +113,5 @@ abstract class LazyModuleImp(outer: LazyModule) extends Module
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suggestName(outer.instanceName)
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outer.instantiate()
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implicit val p = outer.p
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}
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@ -3,6 +3,7 @@
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package diplomacy
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import Chisel._
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import config._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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@ -15,7 +16,7 @@ trait InwardNodeImp[DI, UI, EI, BI <: Data]
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def edgeI(pd: DI, pu: UI): EI
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def bundleI(ei: Seq[EI]): Vec[BI]
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def colour: String
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def connect(bo: => BI, bi: => BI, e: => EI)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit)
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def connect(bo: => BI, bi: => BI, e: => EI)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit)
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// optional methods to track node graph
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def mixI(pu: UI, node: InwardNode[DI, UI, BI]): UI = pu // insert node into parameters
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@ -68,8 +69,8 @@ case class NodeHandle[DI, UI, BI <: Data, DO, UO, BO <: Data]
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trait InwardNodeHandle[DI, UI, BI <: Data]
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{
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val inward: InwardNode[DI, UI, BI]
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def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] =
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inward.:=(h)(sourceInfo)
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def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[LazyModule] =
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inward.:=(h)(p, sourceInfo)
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}
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trait InwardNode[DI, UI, BI <: Data] extends BaseNode with InwardNodeHandle[DI, UI, BI]
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@ -174,7 +175,7 @@ class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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lazy val bundleIn = wireI(flipI(inner.bundleI(edgesIn)))
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// connects the outward part of a node with the inward part of this node
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override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = {
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override def := (h: OutwardNodeHandle[DI, UI, BI])(implicit p: Parameters, sourceInfo: SourceInfo): Option[LazyModule] = {
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val x = this // x := y
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val y = h.outward
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val info = sourceLine(sourceInfo, " at ", "")
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@ -8,11 +8,10 @@ import config._
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import rocketchip._
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import util._
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class TestHarness(q: Parameters) extends Module {
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class TestHarness(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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implicit val p = q
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val dut = Module(LazyModule(new GroundTestTop).module)
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io.success := dut.io.success
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@ -102,7 +102,7 @@ abstract class GroundTest(implicit val p: Parameters) extends Module
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val io = new GroundTestIO
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}
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class GroundTestTile(implicit val p: Parameters) extends LazyModule with HasGroundTestParameters {
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class GroundTestTile(implicit p: Parameters) extends LazyModule with HasGroundTestParameters {
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val dcacheParams = p.alterPartial {
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case CacheName => CacheName("L1D")
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case rocket.TLCacheEdge => cachedOut.edgesOut(0)
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@ -42,7 +42,7 @@ class DCache(cfg: DCacheConfig, val scratch: () => Option[AddressSet])(implicit
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override lazy val module = new DCacheModule(this)
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}
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class DCacheModule(outer: DCache)(implicit p: Parameters) extends HellaCacheModule(outer)(p) {
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class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val maxUncachedInFlight = cfg.nMMIOs
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@ -129,7 +129,7 @@ class HellaCacheIO(implicit p: Parameters) extends CoreBundle()(p) {
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val ordered = Bool(INPUT)
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}
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abstract class HellaCache(val cfg: DCacheConfig)(implicit val p: Parameters) extends LazyModule {
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abstract class HellaCache(val cfg: DCacheConfig)(implicit p: Parameters) extends LazyModule {
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val node = TLClientNode(TLClientParameters(
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sourceId = IdRange(0, cfg.nMSHRs + cfg.nMMIOs),
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supportsProbe = TransferSizes(p(CacheBlockBytes))))
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@ -142,7 +142,7 @@ class HellaCacheBundle(outer: HellaCache)(implicit p: Parameters) extends Bundle
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val mem = outer.node.bundleOut
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}
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class HellaCacheModule(outer: HellaCache)(implicit val p: Parameters) extends LazyModuleImp(outer)
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class HellaCacheModule(outer: HellaCache) extends LazyModuleImp(outer)
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with HasL1HellaCacheParameters {
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implicit val cfg = outer.cfg
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val io = new HellaCacheBundle(outer)
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@ -675,7 +675,7 @@ class NonBlockingDCache(cfg: DCacheConfig)(implicit p: Parameters) extends Hella
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override lazy val module = new NonBlockingDCacheModule(this)
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}
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class NonBlockingDCacheModule(outer: NonBlockingDCache)(implicit p: Parameters) extends HellaCacheModule(outer)(p) {
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class NonBlockingDCacheModule(outer: NonBlockingDCache) extends HellaCacheModule(outer) {
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require(isPow2(nWays)) // TODO: relax this
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require(p(DataScratchpadSize) == 0)
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@ -11,7 +11,7 @@ import uncore.constants._
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import uncore.tilelink2._
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import uncore.util._
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class ScratchpadSlavePort(implicit val p: Parameters) extends LazyModule {
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class ScratchpadSlavePort(implicit p: Parameters) extends LazyModule {
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val coreDataBytes = p(XLen)/8
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val node = TLManagerNode(TLManagerPortParameters(
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Seq(TLManagerParameters(
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@ -12,15 +12,13 @@ import uncore.devices._
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import util._
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import rocket._
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/** Enable or disable monitoring of Diplomatic buses */
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case object TLEmitMonitors extends Field[Boolean]
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abstract class BareTop(implicit val p: Parameters) extends LazyModule {
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abstract class BareTop(implicit p: Parameters) extends LazyModule {
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TopModule.contents = Some(this)
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}
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abstract class BareTopBundle[+L <: BareTop](_outer: L) extends Bundle {
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abstract class BareTopBundle[+L <: BareTop](_outer: L) extends GenericParameterizedBundle(_outer) {
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val outer = _outer
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implicit val p = outer.p
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}
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abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _io: () => B) extends LazyModuleImp(_outer) {
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@ -32,8 +30,6 @@ abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _
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trait TopNetwork extends HasPeripheryParameters {
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val module: TopNetworkModule
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TLImp.emitMonitors = p(TLEmitMonitors)
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// Add a SoC and peripheral bus
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val socBus = LazyModule(new TLXbar)
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val peripheryBus = LazyModule(new TLXbar)
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@ -47,13 +43,11 @@ trait TopNetwork extends HasPeripheryParameters {
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trait TopNetworkBundle extends HasPeripheryParameters {
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val outer: TopNetwork
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implicit val p = outer.p
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}
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trait TopNetworkModule extends HasPeripheryParameters {
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val io: TopNetworkBundle
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val outer: TopNetwork
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implicit val p = outer.p
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}
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/** Base Top with no Periphery */
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@ -8,7 +8,7 @@ import junctions._
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import rocket._
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import diplomacy._
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import uncore.agents._
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import uncore.tilelink._
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import uncore.tilelink2._
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import uncore.devices._
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import uncore.converters._
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import util._
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@ -21,8 +21,11 @@ import config._
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class BasePlatformConfig extends Config(
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(pname,site,here) => pname match {
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// TileLink connection parameters
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case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
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case TLFuzzReadyValid => false
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case TLCombinationalCheck => false
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//Memory Parameters
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case TLEmitMonitors => true
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case NExtTopInterrupts => 2
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case SOCBusConfig => site(L1toL2Config)
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case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
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@ -143,16 +146,9 @@ class With64BitPeriphery extends Config (
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}
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)
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class WithTLMonitors extends Config (
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(pname, site, here) => pname match {
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case TLEmitMonitors => true
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case _ => throw new CDEMatchError
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}
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)
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class WithoutTLMonitors extends Config (
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(pname, site, here) => pname match {
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case TLEmitMonitors => false
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case TLMonitorBuilder => (args: TLMonitorArgs) => None
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case _ => throw new CDEMatchError
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}
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)
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@ -9,11 +9,10 @@ import diplomacy._
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import coreplex._
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import uncore.axi4._
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class TestHarness(q: Parameters) extends Module {
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class TestHarness()(implicit p: Parameters) extends Module {
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val io = new Bundle {
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val success = Bool(OUTPUT)
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}
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implicit val p = q
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val dut = Module(LazyModule(new ExampleRocketTop).module)
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for (int <- dut.io.interrupts(0))
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@ -4,11 +4,12 @@ package uncore.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import config._
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import diplomacy._
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import scala.math.max
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// pipe is only used if a queue has depth = 1
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class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, pipe: Boolean = true) extends LazyModule
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class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule
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{
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require (aw >= 0)
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require (w >= 0)
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@ -37,12 +38,12 @@ class AXI4Buffer(aw: Int = 2, w: Int = 2, b: Int = 2, ar: Int = 2, r: Int = 2, p
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object AXI4Buffer
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{
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// applied to the AXI4 source node; y.node := AXI4Buffer(x.node)
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def apply() (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(2)(x)
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def apply(entries: Int) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, true)(x)
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def apply(entries: Int, pipe: Boolean) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, entries, pipe)(x)
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def apply(aw: Int, br: Int) (x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, br, true)(x)
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def apply(aw: Int, br: Int, pipe: Boolean)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br, pipe)(x)
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def apply(aw: Int, w: Int, b: Int, ar: Int, r: Int, pipe: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
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def apply() (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(2)(x)
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def apply(entries: Int) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, true)(x)
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def apply(entries: Int, pipe: Boolean) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(entries, entries, pipe)(x)
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def apply(aw: Int, br: Int) (x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, br, true)(x)
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def apply(aw: Int, br: Int, pipe: Boolean)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = apply(aw, aw, br, aw, br, pipe)(x)
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def apply(aw: Int, w: Int, b: Int, ar: Int, r: Int, pipe: Boolean = true)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val buffer = LazyModule(new AXI4Buffer(aw, w, b, ar, r, pipe))
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buffer.node := x
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buffer.node
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@ -5,12 +5,13 @@ package uncore.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import chisel3.util.IrrevocableIO
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import config._
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import diplomacy._
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import scala.math.{min,max}
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import uncore.tilelink2.{leftOR, rightOR, UIntToOH1, OH1ToOH}
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// lite: masters all use only one ID => reads will not be interleaved
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class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true) extends LazyModule
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class AXI4Fragmenter(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
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{
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val maxBeats = 1 << AXI4Parameters.lenBits
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def expandTransfer(x: TransferSizes, beatBytes: Int, alignment: BigInt) =
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@ -287,7 +288,7 @@ class AXI4FragmenterSideband(maxInFlight: Int, flow: Boolean = false) extends Mo
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object AXI4Fragmenter
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{
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// applied to the AXI4 source node; y.node := AXI4Fragmenter()(x.node)
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def apply(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
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def apply(lite: Boolean = false, maxInFlight: => Int = 32, combinational: Boolean = true)(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
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val fragmenter = LazyModule(new AXI4Fragmenter(lite, maxInFlight, combinational))
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fragmenter.node := x
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fragmenter.node
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@ -4,6 +4,7 @@ package uncore.axi4
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import config._
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import diplomacy._
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object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters, AXI4EdgeParameters, AXI4EdgeParameters, AXI4Bundle]
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@ -23,7 +24,7 @@ object AXI4Imp extends NodeImp[AXI4MasterPortParameters, AXI4SlavePortParameters
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override def labelI(ei: AXI4EdgeParameters) = (ei.slave.beatBytes * 8).toString
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override def labelO(eo: AXI4EdgeParameters) = (eo.slave.beatBytes * 8).toString
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def connect(bo: => AXI4Bundle, bi: => AXI4Bundle, ei: => AXI4EdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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def connect(bo: => AXI4Bundle, bi: => AXI4Bundle, ei: => AXI4EdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => { bi <> bo })
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}
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@ -3,6 +3,7 @@
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package uncore.axi4
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import Chisel._
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import config._
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import diplomacy._
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import scala.math.max
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@ -3,6 +3,7 @@
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package uncore.axi4
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import Chisel._
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import config._
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import diplomacy._
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import regmapper._
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import scala.math.{min,max}
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@ -77,16 +78,17 @@ object AXI4RegisterNode
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// These convenience methods below combine to make it possible to create a AXI4
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// register mapped device from a totally abstract register mapped device.
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abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule
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abstract class AXI4RegisterRouterBase(address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
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{
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val node = AXI4RegisterNode(address, concurrency, beatBytes, undefZero, executable)
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val intnode = uncore.tilelink2.IntSourceNode(interrupts)
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}
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case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])
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case class AXI4RegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[AXI4Bundle])(implicit val p: Parameters)
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class AXI4RegBundleBase(arg: AXI4RegBundleArg) extends Bundle
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{
|
||||
implicit val p = arg.p
|
||||
val interrupts = arg.interrupts
|
||||
val in = arg.in
|
||||
}
|
||||
@ -104,7 +106,7 @@ class AXI4RegModule[P, B <: AXI4RegBundleBase](val params: P, bundleBuilder: =>
|
||||
class AXI4RegisterRouter[B <: AXI4RegBundleBase, M <: LazyModuleImp]
|
||||
(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
|
||||
(bundleBuilder: AXI4RegBundleArg => B)
|
||||
(moduleBuilder: (=> B, AXI4RegisterRouterBase) => M)
|
||||
(moduleBuilder: (=> B, AXI4RegisterRouterBase) => M)(implicit p: Parameters)
|
||||
extends AXI4RegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
|
||||
{
|
||||
require (isPow2(size))
|
||||
|
@ -3,9 +3,10 @@
|
||||
package uncore.axi4
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
|
||||
class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
|
||||
class AXI4RAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = AXI4SlaveNode(AXI4SlavePortParameters(
|
||||
Seq(AXI4SlaveParameters(
|
||||
|
@ -3,19 +3,20 @@
|
||||
package uncore.axi4
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
import uncore.tilelink2._
|
||||
import unittest._
|
||||
|
||||
class RRTest0(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 0, 4)(
|
||||
class RRTest0(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRouter(address, 0, 32, 0, 4)(
|
||||
new AXI4RegBundle((), _) with RRTest0Bundle)(
|
||||
new AXI4RegModule((), _, _) with RRTest0Module)
|
||||
|
||||
class RRTest1(address: BigInt) extends AXI4RegisterRouter(address, 0, 32, 6, 4, false)(
|
||||
class RRTest1(address: BigInt)(implicit p: Parameters) extends AXI4RegisterRouter(address, 0, 32, 6, 4, false)(
|
||||
new AXI4RegBundle((), _) with RRTest1Bundle)(
|
||||
new AXI4RegModule((), _, _) with RRTest1Module)
|
||||
|
||||
class AXI4LiteFuzzRAM extends LazyModule
|
||||
class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel("AXI4LiteFuzzRAM"))
|
||||
@ -33,12 +34,12 @@ class AXI4LiteFuzzRAM extends LazyModule
|
||||
}
|
||||
}
|
||||
|
||||
class AXI4LiteFuzzRAMTest extends UnitTest(500000) {
|
||||
class AXI4LiteFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) {
|
||||
val dut = Module(LazyModule(new AXI4LiteFuzzRAM).module)
|
||||
io.finished := dut.io.finished
|
||||
}
|
||||
|
||||
class AXI4FullFuzzRAM extends LazyModule
|
||||
class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel("AXI4FullFuzzRAM"))
|
||||
@ -56,12 +57,12 @@ class AXI4FullFuzzRAM extends LazyModule
|
||||
}
|
||||
}
|
||||
|
||||
class AXI4FullFuzzRAMTest extends UnitTest(500000) {
|
||||
class AXI4FullFuzzRAMTest(implicit p: Parameters) extends UnitTest(500000) {
|
||||
val dut = Module(LazyModule(new AXI4FullFuzzRAM).module)
|
||||
io.finished := dut.io.finished
|
||||
}
|
||||
|
||||
class AXI4FuzzMaster extends LazyModule
|
||||
class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = AXI4OutputNode()
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
@ -80,7 +81,7 @@ class AXI4FuzzMaster extends LazyModule
|
||||
}
|
||||
}
|
||||
|
||||
class AXI4FuzzSlave extends LazyModule
|
||||
class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = AXI4InputNode()
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff)))
|
||||
@ -94,7 +95,7 @@ class AXI4FuzzSlave extends LazyModule
|
||||
}
|
||||
}
|
||||
|
||||
class AXI4FuzzBridge extends LazyModule
|
||||
class AXI4FuzzBridge()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val master = LazyModule(new AXI4FuzzMaster)
|
||||
val slave = LazyModule(new AXI4FuzzSlave)
|
||||
@ -106,7 +107,7 @@ class AXI4FuzzBridge extends LazyModule
|
||||
}
|
||||
}
|
||||
|
||||
class AXI4BridgeTest extends UnitTest(500000) {
|
||||
class AXI4BridgeTest()(implicit p: Parameters) extends UnitTest(500000) {
|
||||
val dut = Module(LazyModule(new AXI4FuzzBridge).module)
|
||||
io.finished := dut.io.finished
|
||||
}
|
||||
|
@ -4,6 +4,7 @@ package uncore.axi4
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import uncore.tilelink2._
|
||||
|
||||
@ -30,7 +31,7 @@ case class AXI4ToTLNode() extends MixedNode(AXI4Imp, TLImp)(
|
||||
numPO = 1 to 1,
|
||||
numPI = 1 to 1)
|
||||
|
||||
class AXI4ToTL extends LazyModule
|
||||
class AXI4ToTL()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = AXI4ToTLNode()
|
||||
|
||||
@ -176,7 +177,7 @@ class AXI4BundleRError(params: AXI4BundleParameters) extends AXI4BundleBase(para
|
||||
|
||||
object AXI4ToTL
|
||||
{
|
||||
def apply()(x: AXI4OutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply()(x: AXI4OutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val tl = LazyModule(new AXI4ToTL)
|
||||
tl.node := x
|
||||
tl.node
|
||||
|
@ -332,8 +332,7 @@ object ToAsyncDebugBus
|
||||
}
|
||||
|
||||
trait HasDebugModuleParameters {
|
||||
val params : Parameters
|
||||
implicit val p = params
|
||||
implicit val p: Parameters
|
||||
val cfg = p(DMKey)
|
||||
}
|
||||
|
||||
@ -850,8 +849,8 @@ trait DebugModule extends Module with HasDebugModuleParameters with HasRegMap {
|
||||
|
||||
class TLDebugModule(address: BigInt = 0)(implicit p: Parameters)
|
||||
extends TLRegisterRouter(address, beatBytes=p(rocket.XLen)/8, executable=true)(
|
||||
new TLRegBundle(p, _ ) with DebugModuleBundle)(
|
||||
new TLRegModule(p, _, _) with DebugModule)
|
||||
new TLRegBundle((), _ ) with DebugModuleBundle)(
|
||||
new TLRegModule((), _, _) with DebugModule)
|
||||
|
||||
|
||||
/** Synchronizers for DebugBus
|
||||
|
@ -52,7 +52,7 @@ object PLICConsts
|
||||
}
|
||||
|
||||
/** Platform-Level Interrupt Controller */
|
||||
class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit val p: Parameters) extends LazyModule
|
||||
class TLPLIC(supervisor: Boolean, maxPriorities: Int, address: BigInt = 0xC000000)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val contextsPerHart = if (supervisor) 2 else 1
|
||||
require (maxPriorities >= 0)
|
||||
|
@ -32,8 +32,7 @@ object ClintConsts
|
||||
}
|
||||
|
||||
trait MixCoreplexLocalInterrupterParameters {
|
||||
val params: Parameters
|
||||
implicit val p = params
|
||||
implicit val p: Parameters
|
||||
}
|
||||
|
||||
trait CoreplexLocalInterrupterBundle extends Bundle with MixCoreplexLocalInterrupterParameters {
|
||||
@ -83,10 +82,10 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
|
||||
|
||||
/** Power, Reset, Clock, Interrupt */
|
||||
// Magic TL2 Incantation to create a TL2 Slave
|
||||
class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Parameters)
|
||||
class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit p: Parameters)
|
||||
extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = true)(
|
||||
new TLRegBundle(p, _) with CoreplexLocalInterrupterBundle)(
|
||||
new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule)
|
||||
new TLRegBundle((), _) with CoreplexLocalInterrupterBundle)(
|
||||
new TLRegModule((), _, _) with CoreplexLocalInterrupterModule)
|
||||
{
|
||||
val globalConfigString = Seq(
|
||||
s"rtc {\n",
|
||||
|
@ -12,7 +12,7 @@ import uncore.tilelink2._
|
||||
import uncore.util._
|
||||
import config._
|
||||
|
||||
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
|
||||
class TLROM(val base: BigInt, val size: Int, contentsDelayed: => Seq[Byte], executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLManagerNode(beatBytes, TLManagerParameters(
|
||||
address = List(AddressSet(base, size-1)),
|
||||
|
@ -4,12 +4,13 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.math.{min,max}
|
||||
|
||||
// Ensures that all downstream RW managers support Atomic operationss.
|
||||
// If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.
|
||||
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true) extends LazyModule
|
||||
class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
require (concurrency >= 1)
|
||||
|
||||
@ -278,7 +279,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
|
||||
object TLAtomicAutomata
|
||||
{
|
||||
// applied to the TL source node; y.node := TLAtomicAutomata(x.node)
|
||||
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
|
||||
atomics.node := x
|
||||
atomics.node
|
||||
@ -290,7 +291,7 @@ import unittest._
|
||||
|
||||
//TODO ensure handler will pass through operations to clients that can handle them themselves
|
||||
|
||||
class TLRAMAtomicAutomata() extends LazyModule {
|
||||
class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel)
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
@ -303,6 +304,6 @@ class TLRAMAtomicAutomata() extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMAtomicAutomataTest extends UnitTest(timeout = 500000) {
|
||||
class TLRAMAtomicAutomataTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new TLRAMAtomicAutomata).module).io.finished
|
||||
}
|
||||
|
@ -3,10 +3,11 @@
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.math.{min,max}
|
||||
|
||||
class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false) extends LazyModule
|
||||
class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
require (lineBytes > 0 && isPow2(lineBytes))
|
||||
require (numTrackers > 0)
|
||||
|
@ -4,11 +4,12 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.math.{min,max}
|
||||
|
||||
// pipe is only used if a queue has depth = 1
|
||||
class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe: Boolean = true) extends LazyModule
|
||||
class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe: Boolean = true)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
require (a >= 0)
|
||||
require (b >= 0)
|
||||
@ -49,12 +50,12 @@ class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe:
|
||||
object TLBuffer
|
||||
{
|
||||
// applied to the TL source node; y.node := TLBuffer(x.node)
|
||||
def apply() (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(2)(x)
|
||||
def apply(entries: Int) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(entries, true)(x)
|
||||
def apply(entries: Int, pipe: Boolean) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(entries, entries, pipe)(x)
|
||||
def apply(ace: Int, bd: Int) (x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, true)(x)
|
||||
def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace, pipe)(x)
|
||||
def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply() (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(2)(x)
|
||||
def apply(entries: Int) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(entries, true)(x)
|
||||
def apply(entries: Int, pipe: Boolean) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(entries, entries, pipe)(x)
|
||||
def apply(ace: Int, bd: Int) (x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, true)(x)
|
||||
def apply(ace: Int, bd: Int, pipe: Boolean)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = apply(ace, bd, ace, bd, ace, pipe)(x)
|
||||
def apply(a: Int, b: Int, c: Int, d: Int, e: Int, pipe: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val buffer = LazyModule(new TLBuffer(a, b, c, d, e, pipe))
|
||||
buffer.node := x
|
||||
buffer.node
|
||||
|
@ -4,10 +4,11 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import util._
|
||||
|
||||
class TLAsyncCrossingSource(sync: Int = 3) extends LazyModule
|
||||
class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLAsyncSourceNode()
|
||||
|
||||
@ -41,7 +42,7 @@ class TLAsyncCrossingSource(sync: Int = 3) extends LazyModule
|
||||
}
|
||||
}
|
||||
|
||||
class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule
|
||||
class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLAsyncSinkNode(depth)
|
||||
|
||||
@ -77,7 +78,7 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3) extends LazyModule
|
||||
object TLAsyncCrossingSource
|
||||
{
|
||||
// applied to the TL source node; y.node := TLAsyncCrossingSource()(x.node)
|
||||
def apply(sync: Int = 3)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLAsyncOutwardNode = {
|
||||
def apply(sync: Int = 3)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLAsyncOutwardNode = {
|
||||
val source = LazyModule(new TLAsyncCrossingSource(sync))
|
||||
source.node := x
|
||||
source.node
|
||||
@ -87,14 +88,14 @@ object TLAsyncCrossingSource
|
||||
object TLAsyncCrossingSink
|
||||
{
|
||||
// applied to the TL source node; y.node := TLAsyncCrossingSink()(x.node)
|
||||
def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply(depth: Int = 8, sync: Int = 3)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
|
||||
sink.node := x
|
||||
sink.node
|
||||
}
|
||||
}
|
||||
|
||||
class TLAsyncCrossing(depth: Int = 8, sync: Int = 3) extends LazyModule
|
||||
class TLAsyncCrossing(depth: Int = 8, sync: Int = 3)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val nodeIn = TLInputNode()
|
||||
val nodeOut = TLOutputNode()
|
||||
@ -136,7 +137,7 @@ class TLAsyncCrossing(depth: Int = 8, sync: Int = 3) extends LazyModule
|
||||
/** Synthesizeable unit tests */
|
||||
import unittest._
|
||||
|
||||
class TLRAMCrossing extends LazyModule {
|
||||
class TLRAMCrossing(implicit p: Parameters) extends LazyModule {
|
||||
val model = LazyModule(new TLRAMModel)
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
@ -167,6 +168,6 @@ class TLRAMCrossing extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMCrossingTest extends UnitTest(timeout = 500000) {
|
||||
class TLRAMCrossingTest(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new TLRAMCrossing).module).io.finished
|
||||
}
|
||||
|
@ -3,6 +3,7 @@
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import regmapper._
|
||||
|
||||
case class ExampleParams(num: Int, address: BigInt)
|
||||
@ -33,6 +34,6 @@ trait ExampleModule extends HasRegMap
|
||||
}
|
||||
|
||||
// Create a concrete TL2 version of the abstract Example slave
|
||||
class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address, 4)(
|
||||
new TLRegBundle(p, _) with ExampleBundle)(
|
||||
new TLRegModule(p, _, _) with ExampleModule)
|
||||
class TLExample(params: ExampleParams)(implicit p: Parameters) extends TLRegisterRouter(params.address, 4)(
|
||||
new TLRegBundle(params, _) with ExampleBundle)(
|
||||
new TLRegModule(params, _, _) with ExampleModule)
|
||||
|
@ -4,10 +4,11 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.math.{min,max}
|
||||
|
||||
class TLFilter(select: AddressSet) extends LazyModule
|
||||
class TLFilter(select: AddressSet)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLAdapterNode(
|
||||
clientFn = { case Seq(cp) => cp },
|
||||
@ -44,7 +45,7 @@ class TLFilter(select: AddressSet) extends LazyModule
|
||||
object TLFilter
|
||||
{
|
||||
// applied to the TL source node; y.node := TLBuffer(x.node)
|
||||
def apply(select: AddressSet)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply(select: AddressSet)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val filter = LazyModule(new TLFilter(select))
|
||||
filter.node := x
|
||||
filter.node
|
||||
|
@ -4,6 +4,7 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.math.{min,max}
|
||||
|
||||
@ -13,7 +14,7 @@ import scala.math.{min,max}
|
||||
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
|
||||
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
|
||||
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
|
||||
class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) extends LazyModule
|
||||
class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
require (isPow2 (maxSize))
|
||||
require (isPow2 (minSize))
|
||||
@ -253,7 +254,7 @@ class TLFragmenter(minSize: Int, maxSize: Int, alwaysMin: Boolean = false) exten
|
||||
object TLFragmenter
|
||||
{
|
||||
// applied to the TL source node; y.node := TLFragmenter(x.node, 256, 4)
|
||||
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin))
|
||||
fragmenter.node := x
|
||||
fragmenter.node
|
||||
@ -263,7 +264,7 @@ object TLFragmenter
|
||||
/** Synthesizeable unit tests */
|
||||
import unittest._
|
||||
|
||||
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int) extends LazyModule {
|
||||
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel)
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
|
||||
@ -276,6 +277,6 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int) extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int) extends UnitTest(timeout = 500000) {
|
||||
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize)).module).io.finished
|
||||
}
|
||||
|
@ -3,6 +3,7 @@
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
|
||||
class IDMapGenerator(numIds: Int) extends Module {
|
||||
@ -85,7 +86,7 @@ class TLFuzzer(
|
||||
(wide: Int, increment: Bool, abs_values: Int) =>
|
||||
LFSRNoiseMaker(wide=wide, increment=increment)
|
||||
}
|
||||
) extends LazyModule
|
||||
)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLClientNode(TLClientParameters(sourceId = IdRange(0,inFlight)))
|
||||
|
||||
@ -203,7 +204,7 @@ class TLFuzzer(
|
||||
/** Synthesizeable integration test */
|
||||
import unittest._
|
||||
|
||||
class TLFuzzRAM extends LazyModule
|
||||
class TLFuzzRAM()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val model = LazyModule(new TLRAMModel("TLFuzzRAM"))
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x800, 0x7ff)))
|
||||
@ -243,7 +244,7 @@ class TLFuzzRAM extends LazyModule
|
||||
}
|
||||
}
|
||||
|
||||
class TLFuzzRAMTest extends UnitTest(500000) {
|
||||
class TLFuzzRAMTest()(implicit p: Parameters) extends UnitTest(500000) {
|
||||
val dut = Module(LazyModule(new TLFuzzRAM).module)
|
||||
io.finished := dut.io.finished
|
||||
}
|
||||
|
@ -5,10 +5,11 @@ package uncore.tilelink2
|
||||
import scala.math.min
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
|
||||
// Acks Hints for managers that don't support them or Acks all Hints if !passthrough
|
||||
class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true) extends LazyModule
|
||||
class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLAdapterNode(
|
||||
clientFn = { case Seq(c) => if (!supportClients) c else c.copy(minLatency = min(1, c.minLatency), clients = c.clients .map(_.copy(supportsHint = TransferSizes(1, c.maxTransfer)))) },
|
||||
@ -100,7 +101,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
|
||||
object TLHintHandler
|
||||
{
|
||||
// applied to the TL source node; y.node := TLHintHandler(x.node)
|
||||
def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply(supportManagers: Boolean = true, supportClients: Boolean = false, passthrough: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val hints = LazyModule(new TLHintHandler(supportManagers, supportClients, passthrough))
|
||||
hints.node := x
|
||||
hints.node
|
||||
@ -112,7 +113,7 @@ import unittest._
|
||||
|
||||
//TODO ensure handler will pass through hints to clients that can handle them themselves
|
||||
|
||||
class TLRAMHintHandler() extends LazyModule {
|
||||
class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel)
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
@ -125,6 +126,6 @@ class TLRAMHintHandler() extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMHintHandlerTest extends UnitTest(timeout = 500000) {
|
||||
class TLRAMHintHandlerTest()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new TLRAMHintHandler).module).io.finished
|
||||
}
|
||||
|
@ -4,6 +4,7 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.collection.mutable.ListBuffer
|
||||
import scala.math.max
|
||||
@ -65,7 +66,7 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
|
||||
override def labelI(ei: IntEdge) = ei.source.sources.map(_.range.size).sum.toString
|
||||
override def labelO(eo: IntEdge) = eo.source.sources.map(_.range.size).sum.toString
|
||||
|
||||
def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
|
||||
def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
|
||||
(None, () => {
|
||||
// Cannot use bulk connect, because the widths could differ
|
||||
(bo zip bi) foreach { case (o, i) => i := o }
|
||||
@ -100,7 +101,7 @@ case class IntBlindInputNode(num: Int) extends BlindInputNode(IntImp)(IntSourceP
|
||||
case class IntInternalOutputNode() extends InternalOutputNode(IntImp)(IntSinkPortParameters(Seq(IntSinkParameters())))
|
||||
case class IntInternalInputNode(num: Int) extends InternalInputNode(IntImp)(IntSourcePortParameters(Seq(IntSourceParameters(num))))
|
||||
|
||||
class IntXbar extends LazyModule
|
||||
class IntXbar()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val intnode = IntAdapterNode(
|
||||
numSourcePorts = 0 to 128,
|
||||
@ -123,7 +124,7 @@ class IntXbar extends LazyModule
|
||||
}
|
||||
}
|
||||
|
||||
class IntXing extends LazyModule
|
||||
class IntXing()(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val intnode = IntIdentityNode()
|
||||
|
||||
|
@ -4,11 +4,12 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import util.AsyncBundle
|
||||
|
||||
// READ the comments in the TLIsolation object before you instantiate this module
|
||||
class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt) extends LazyModule
|
||||
class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLAsyncIdentityNode()
|
||||
|
||||
@ -76,7 +77,7 @@ object TLIsolation
|
||||
// fOut is applied to data flowing from client to manager
|
||||
// fIn is applied to data flowing from manager to client
|
||||
// **** WARNING: the isolation functions must bring the values to 0 ****
|
||||
def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
|
||||
def apply(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(x: TLAsyncOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): (TLAsyncOutwardNode, () => (Bool, Bool)) = {
|
||||
val iso = LazyModule(new TLIsolation(fOut, fIn))
|
||||
iso.node := x
|
||||
(iso.node, () => (iso.module.io.iso_out, iso.module.io.iso_in))
|
||||
|
@ -8,19 +8,15 @@ import config._
|
||||
import uncore.tilelink._
|
||||
import uncore.constants._
|
||||
|
||||
// Instantiate 'val p' before HasTileLinkParameters tries to use it
|
||||
abstract class LegacyLazyModuleImp(module: LazyModule)(implicit val p: Parameters)
|
||||
extends LazyModuleImp(module) with HasTileLinkParameters
|
||||
|
||||
class TLLegacy(implicit val p: Parameters) extends LazyModule with HasTileLinkParameters
|
||||
class TLLegacy(implicit p: Parameters) extends LazyModule with HasTileLinkParameters
|
||||
{
|
||||
// TL legacy clients don't support anything fancy
|
||||
val node = TLClientNode(TLClientParameters(
|
||||
sourceId = IdRange(0, 1 << tlClientXactIdBits)))
|
||||
|
||||
lazy val module = new LegacyLazyModuleImp(this) {
|
||||
lazy val module = new LazyModuleImp(this) with HasTileLinkParameters {
|
||||
val io = new Bundle {
|
||||
val legacy = new ClientUncachedTileLinkIO()(p).flip
|
||||
val legacy = new ClientUncachedTileLinkIO().flip
|
||||
val out = node.bundleOut
|
||||
}
|
||||
|
||||
|
@ -4,9 +4,27 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
|
||||
import config._
|
||||
import diplomacy._
|
||||
|
||||
class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo) extends LazyModule
|
||||
case class TLMonitorArgs(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo, p: Parameters)
|
||||
|
||||
abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p)
|
||||
{
|
||||
implicit val sourceInfo = args.sourceInfo
|
||||
|
||||
def legalize(bundle: TLBundleSnoop, edge: TLEdge): Unit
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = args.gen().asInput
|
||||
}
|
||||
|
||||
legalize(io.in, args.edge())
|
||||
}
|
||||
}
|
||||
|
||||
class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
|
||||
{
|
||||
def extra(implicit sourceInfo: SourceInfo) = {
|
||||
sourceInfo match {
|
||||
@ -409,17 +427,9 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
|
||||
inflight := (inflight | a_set) & ~d_clr
|
||||
}
|
||||
|
||||
def legalize(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
|
||||
legalizeFormat (bundle, edge)
|
||||
legalizeMultibeat (bundle, edge)
|
||||
def legalize(bundle: TLBundleSnoop, edge: TLEdge) {
|
||||
legalizeFormat (bundle, edge)
|
||||
legalizeMultibeat (bundle, edge)
|
||||
legalizeSourceUnique(bundle, edge)
|
||||
}
|
||||
|
||||
lazy val module = new LazyModuleImp(this) {
|
||||
val io = new Bundle {
|
||||
val in = gen().asInput
|
||||
}
|
||||
|
||||
legalize(io.in, edge())(sourceInfo)
|
||||
}
|
||||
}
|
||||
|
@ -4,9 +4,14 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.collection.mutable.ListBuffer
|
||||
|
||||
case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]]
|
||||
case object TLFuzzReadyValid extends Field[Boolean]
|
||||
case object TLCombinationalCheck extends Field[Boolean]
|
||||
|
||||
object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
|
||||
{
|
||||
def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
|
||||
@ -20,24 +25,16 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
|
||||
Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_))))
|
||||
}
|
||||
|
||||
var emitMonitors = true
|
||||
var stressTestDecoupled = false
|
||||
var combinationalCheck = false
|
||||
|
||||
def colour = "#000000" // black
|
||||
override def labelI(ei: TLEdgeIn) = (ei.manager.beatBytes * 8).toString
|
||||
override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString
|
||||
|
||||
def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
|
||||
val monitor = if (emitMonitors) {
|
||||
Some(LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)))
|
||||
} else {
|
||||
None
|
||||
}
|
||||
def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
|
||||
val monitor = p(TLMonitorBuilder)(TLMonitorArgs(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo, p))
|
||||
(monitor, () => {
|
||||
bi <> bo
|
||||
monitor.foreach { _.module.io.in := TLBundleSnoop(bo) }
|
||||
if (combinationalCheck) {
|
||||
if (p(TLCombinationalCheck)) {
|
||||
// It is forbidden for valid to depend on ready in TL2
|
||||
// If someone did that, then this will create a detectable combinational loop
|
||||
bo.a.ready := bi.a.ready && bo.a.valid
|
||||
@ -46,7 +43,7 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
|
||||
bi.d.ready := bo.d.ready && bi.d.valid
|
||||
bo.e.ready := bi.e.ready && bo.e.valid
|
||||
}
|
||||
if (stressTestDecoupled) {
|
||||
if (p(TLCombinationalCheck)) {
|
||||
// Randomly stall the transfers
|
||||
val allow = LFSRNoiseMaker(5)
|
||||
bi.a.valid := bo.a.valid && allow(0)
|
||||
@ -132,7 +129,7 @@ case class TLInternalInputNode(portParams: TLClientPortParameters) extends Inter
|
||||
/** Synthesizeable unit tests */
|
||||
import unittest._
|
||||
|
||||
class TLInputNodeTest extends UnitTest(500000) {
|
||||
class TLInputNodeTest()(implicit p: Parameters) extends UnitTest(500000) {
|
||||
class Acceptor extends LazyModule {
|
||||
val node = TLInputNode()
|
||||
val tlram = LazyModule(new TLRAM(AddressSet(0x54321000, 0xfff)))
|
||||
@ -168,7 +165,7 @@ object TLAsyncImp extends NodeImp[TLAsyncClientPortParameters, TLAsyncManagerPor
|
||||
override def labelI(ei: TLAsyncEdgeParameters) = ei.manager.depth.toString
|
||||
override def labelO(eo: TLAsyncEdgeParameters) = eo.manager.depth.toString
|
||||
|
||||
def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
|
||||
def connect(bo: => TLAsyncBundle, bi: => TLAsyncBundle, ei: => TLAsyncEdgeParameters)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
|
||||
(None, () => { bi <> bo })
|
||||
}
|
||||
|
||||
|
@ -3,6 +3,7 @@
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
|
||||
// We detect concurrent puts that put memory into an undefined state.
|
||||
@ -20,7 +21,7 @@ import diplomacy._
|
||||
// put, get, getAck, putAck => ok: detected by getAck (it sees busy>0) impossible for FIFO
|
||||
// If FIFO, the getAck should check data even if its validity was wiped
|
||||
|
||||
class TLRAMModel(log: String = "") extends LazyModule
|
||||
class TLRAMModel(log: String = "")(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLIdentityNode()
|
||||
|
||||
|
@ -3,6 +3,7 @@
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
import regmapper._
|
||||
import scala.math.{min,max}
|
||||
@ -79,21 +80,22 @@ object TLRegisterNode
|
||||
// register mapped device from a totally abstract register mapped device.
|
||||
// See GPIO.scala in this directory for an example
|
||||
|
||||
abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean) extends LazyModule
|
||||
abstract class TLRegisterRouterBase(val address: AddressSet, interrupts: Int, concurrency: Int, beatBytes: Int, undefZero: Boolean, executable: Boolean)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLRegisterNode(address, concurrency, beatBytes, undefZero, executable)
|
||||
val intnode = IntSourceNode(interrupts)
|
||||
}
|
||||
|
||||
case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])
|
||||
case class TLRegBundleArg(interrupts: Vec[Vec[Bool]], in: Vec[TLBundle])(implicit val p: Parameters)
|
||||
|
||||
class TLRegBundleBase(arg: TLRegBundleArg) extends Bundle
|
||||
{
|
||||
implicit val p = arg.p
|
||||
val interrupts = arg.interrupts
|
||||
val in = arg.in
|
||||
}
|
||||
|
||||
class TLRegBundle[P](val params: P, arg: TLRegBundleArg) extends TLRegBundleBase(arg)
|
||||
class TLRegBundle[P](val params: P, arg: TLRegBundleArg)(implicit p: Parameters) extends TLRegBundleBase(arg)
|
||||
|
||||
class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, router: TLRegisterRouterBase)
|
||||
extends LazyModuleImp(router) with HasRegMap
|
||||
@ -107,7 +109,7 @@ class TLRegModule[P, B <: TLRegBundleBase](val params: P, bundleBuilder: => B, r
|
||||
class TLRegisterRouter[B <: TLRegBundleBase, M <: LazyModuleImp]
|
||||
(val base: BigInt, val interrupts: Int = 0, val size: BigInt = 4096, val concurrency: Int = 0, val beatBytes: Int = 4, undefZero: Boolean = true, executable: Boolean = false)
|
||||
(bundleBuilder: TLRegBundleArg => B)
|
||||
(moduleBuilder: (=> B, TLRegisterRouterBase) => M)
|
||||
(moduleBuilder: (=> B, TLRegisterRouterBase) => M)(implicit p: Parameters)
|
||||
extends TLRegisterRouterBase(AddressSet(base, size-1), interrupts, concurrency, beatBytes, undefZero, executable)
|
||||
{
|
||||
require (isPow2(size))
|
||||
|
@ -3,6 +3,7 @@
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
import regmapper._
|
||||
import unittest._
|
||||
@ -213,7 +214,7 @@ trait RRTest0Module extends HasRegMap
|
||||
regmap(RRTest0Map.map:_*)
|
||||
}
|
||||
|
||||
class RRTest0(address: BigInt) extends TLRegisterRouter(address, 0, 32, 0, 4)(
|
||||
class RRTest0(address: BigInt)(implicit p: Parameters) extends TLRegisterRouter(address, 0, 32, 0, 4)(
|
||||
new TLRegBundle((), _) with RRTest0Bundle)(
|
||||
new TLRegModule((), _, _) with RRTest0Module)
|
||||
|
||||
@ -250,11 +251,11 @@ trait RRTest1Module extends Module with HasRegMap
|
||||
regmap(map:_*)
|
||||
}
|
||||
|
||||
class RRTest1(address: BigInt) extends TLRegisterRouter(address, 0, 32, 6, 4)(
|
||||
class RRTest1(address: BigInt)(implicit p: Parameters) extends TLRegisterRouter(address, 0, 32, 6, 4)(
|
||||
new TLRegBundle((), _) with RRTest1Bundle)(
|
||||
new TLRegModule((), _, _) with RRTest1Module)
|
||||
|
||||
class FuzzRRTest0 extends LazyModule {
|
||||
class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val rrtr = LazyModule(new RRTest0(0x400))
|
||||
|
||||
@ -265,11 +266,11 @@ class FuzzRRTest0 extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRR0Test extends UnitTest(timeout = 500000) {
|
||||
class TLRR0Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new FuzzRRTest0).module).io.finished
|
||||
}
|
||||
|
||||
class FuzzRRTest1 extends LazyModule {
|
||||
class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val rrtr = LazyModule(new RRTest1(0x400))
|
||||
|
||||
@ -280,7 +281,7 @@ class FuzzRRTest1 extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRR1Test extends UnitTest(timeout = 500000) {
|
||||
class TLRR1Test()(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new FuzzRRTest1).module).io.finished
|
||||
}
|
||||
|
||||
|
@ -3,9 +3,10 @@
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
|
||||
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4) extends LazyModule
|
||||
class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLManagerNode(TLManagerPortParameters(
|
||||
Seq(TLManagerParameters(
|
||||
@ -84,7 +85,7 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
|
||||
/** Synthesizeable unit testing */
|
||||
import unittest._
|
||||
|
||||
class TLRAMSimple(ramBeatBytes: Int) extends LazyModule {
|
||||
class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel)
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
|
||||
@ -97,6 +98,6 @@ class TLRAMSimple(ramBeatBytes: Int) extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMSimpleTest(ramBeatBytes: Int) extends UnitTest(timeout = 500000) {
|
||||
class TLRAMSimpleTest(ramBeatBytes: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new TLRAMSimple(ramBeatBytes)).module).io.finished
|
||||
}
|
||||
|
@ -4,10 +4,11 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.math.{min,max}
|
||||
|
||||
class TLSourceShrinker(maxInFlight: Int) extends LazyModule
|
||||
class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
require (maxInFlight > 0)
|
||||
|
||||
@ -78,7 +79,7 @@ class TLSourceShrinker(maxInFlight: Int) extends LazyModule
|
||||
object TLSourceShrinker
|
||||
{
|
||||
// applied to the TL source node; y.node := TLSourceShrinker(n)(x.node)
|
||||
def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply(maxInFlight: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val shrinker = LazyModule(new TLSourceShrinker(maxInFlight))
|
||||
shrinker.node := x
|
||||
shrinker.node
|
||||
|
@ -4,6 +4,7 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import util.PositionalMultiQueue
|
||||
import uncore.axi4._
|
||||
@ -35,7 +36,7 @@ case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
|
||||
numPO = 1 to 1,
|
||||
numPI = 1 to 1)
|
||||
|
||||
class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
|
||||
class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLToAXI4Node(idBits)
|
||||
|
||||
@ -229,7 +230,7 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true) extends LazyModule
|
||||
object TLToAXI4
|
||||
{
|
||||
// applied to the TL source node; y.node := TLToAXI4(idBits)(x.node)
|
||||
def apply(idBits: Int, combinational: Boolean = true)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): AXI4OutwardNode = {
|
||||
def apply(idBits: Int, combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AXI4OutwardNode = {
|
||||
val axi4 = LazyModule(new TLToAXI4(idBits, combinational))
|
||||
axi4.node := x
|
||||
axi4.node
|
||||
|
@ -4,11 +4,12 @@ package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import chisel3.internal.sourceinfo.SourceInfo
|
||||
import config._
|
||||
import diplomacy._
|
||||
import scala.math.{min,max}
|
||||
|
||||
// innBeatBytes => the new client-facing bus width
|
||||
class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
|
||||
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
val node = TLAdapterNode(
|
||||
clientFn = { case Seq(c) => c },
|
||||
@ -166,7 +167,7 @@ class TLWidthWidget(innerBeatBytes: Int) extends LazyModule
|
||||
object TLWidthWidget
|
||||
{
|
||||
// applied to the TL source node; y.node := WidthWidget(x.node, 16)
|
||||
def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
def apply(innerBeatBytes: Int)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
|
||||
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
|
||||
widget.node := x
|
||||
widget.node
|
||||
@ -176,7 +177,7 @@ object TLWidthWidget
|
||||
/** Synthesizeable unit tests */
|
||||
import unittest._
|
||||
|
||||
class TLRAMWidthWidget(first: Int, second: Int) extends LazyModule {
|
||||
class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel)
|
||||
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
|
||||
@ -193,6 +194,6 @@ class TLRAMWidthWidget(first: Int, second: Int) extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMWidthWidgetTest(little: Int, big: Int) extends UnitTest(timeout = 500000) {
|
||||
class TLRAMWidthWidgetTest(little: Int, big: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new TLRAMWidthWidget(little,big)).module).io.finished
|
||||
}
|
||||
|
@ -3,9 +3,10 @@
|
||||
package uncore.tilelink2
|
||||
|
||||
import Chisel._
|
||||
import config._
|
||||
import diplomacy._
|
||||
|
||||
class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends LazyModule
|
||||
class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p: Parameters) extends LazyModule
|
||||
{
|
||||
def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId))
|
||||
def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
|
||||
@ -184,7 +185,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst) extends Lazy
|
||||
/** Synthesizeable unit tests */
|
||||
import unittest._
|
||||
|
||||
class TLRAMXbar(nManagers: Int) extends LazyModule {
|
||||
class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val fuzz = LazyModule(new TLFuzzer(5000))
|
||||
val model = LazyModule(new TLRAMModel)
|
||||
val xbar = LazyModule(new TLXbar)
|
||||
@ -201,11 +202,11 @@ class TLRAMXbar(nManagers: Int) extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLRAMXbarTest(nManagers: Int) extends UnitTest(timeout = 500000) {
|
||||
class TLRAMXbarTest(nManagers: Int)(implicit p: Parameters) extends UnitTest(timeout = 500000) {
|
||||
io.finished := Module(LazyModule(new TLRAMXbar(nManagers)).module).io.finished
|
||||
}
|
||||
|
||||
class TLMulticlientXbar(nManagers: Int, nClients: Int) extends LazyModule {
|
||||
class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) extends LazyModule {
|
||||
val xbar = LazyModule(new TLXbar)
|
||||
|
||||
val fuzzers = (0 until nClients) map { n =>
|
||||
@ -224,6 +225,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int) extends LazyModule {
|
||||
}
|
||||
}
|
||||
|
||||
class TLMulticlientXbarTest(nManagers: Int, nClients: Int) extends UnitTest(timeout = 5000000) {
|
||||
class TLMulticlientXbarTest(nManagers: Int, nClients: Int)(implicit p: Parameters) extends UnitTest(timeout = 5000000) {
|
||||
io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients)).module).io.finished
|
||||
}
|
||||
|
@ -25,14 +25,16 @@ class JunctionsUnitTestConfig extends Config(new WithJunctionsUnitTests ++ new B
|
||||
class WithUncoreUnitTests extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case uncore.tilelink.TLId => "L1toL2"
|
||||
case UnitTests => (p: Parameters) => Seq(
|
||||
Module(new uncore.devices.ROMSlaveTest()(p)),
|
||||
Module(new uncore.devices.TileLinkRAMTest()(p)),
|
||||
Module(new uncore.converters.TileLinkWidthAdapterTest()(p)),
|
||||
Module(new uncore.tilelink2.TLFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4FullFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4BridgeTest))
|
||||
case UnitTests => (q: Parameters) => {
|
||||
implicit val p = q
|
||||
Seq(
|
||||
Module(new uncore.devices.ROMSlaveTest()),
|
||||
Module(new uncore.devices.TileLinkRAMTest()),
|
||||
Module(new uncore.converters.TileLinkWidthAdapterTest()),
|
||||
Module(new uncore.tilelink2.TLFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4LiteFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4FullFuzzRAMTest),
|
||||
Module(new uncore.axi4.AXI4BridgeTest)) }
|
||||
case _ => throw new CDEMatchError
|
||||
}
|
||||
)
|
||||
@ -41,7 +43,8 @@ class UncoreUnitTestConfig extends Config(new WithUncoreUnitTests ++ new BaseCon
|
||||
|
||||
class WithTLSimpleUnitTests extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case UnitTests => (p: Parameters) => {
|
||||
case UnitTests => (q: Parameters) => {
|
||||
implicit val p = q
|
||||
Seq(
|
||||
Module(new uncore.tilelink2.TLRAMSimpleTest(1)),
|
||||
Module(new uncore.tilelink2.TLRAMSimpleTest(4)),
|
||||
@ -53,7 +56,9 @@ class WithTLSimpleUnitTests extends Config(
|
||||
|
||||
class WithTLWidthUnitTests extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case UnitTests => (p: Parameters) => { Seq(
|
||||
case UnitTests => (q: Parameters) => {
|
||||
implicit val p = q
|
||||
Seq(
|
||||
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 256)),
|
||||
Module(new uncore.tilelink2.TLRAMFragmenterTest(16, 64)),
|
||||
Module(new uncore.tilelink2.TLRAMFragmenterTest( 4, 16)),
|
||||
@ -64,7 +69,9 @@ class WithTLWidthUnitTests extends Config(
|
||||
|
||||
class WithTLXbarUnitTests extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case UnitTests => (p: Parameters) => { Seq(
|
||||
case UnitTests => (q: Parameters) => {
|
||||
implicit val p = q
|
||||
Seq(
|
||||
Module(new uncore.tilelink2.TLRAMXbarTest(1)),
|
||||
Module(new uncore.tilelink2.TLRAMXbarTest(2)),
|
||||
Module(new uncore.tilelink2.TLRAMXbarTest(8)),
|
||||
|
@ -4,7 +4,7 @@ package util
|
||||
|
||||
import Chisel._
|
||||
|
||||
abstract class GenericParameterizedBundle[T <: Object](val params: T) extends Bundle
|
||||
abstract class GenericParameterizedBundle[+T <: Object](val params: T) extends Bundle
|
||||
{
|
||||
override def cloneType = {
|
||||
try {
|
||||
|
Loading…
Reference in New Issue
Block a user