rocketchip: add a parameter-controlled debug port

src/main/scala/rocketchip/RISCVPlatform.scala

@@ -11,6 +11,8 @@ import util._
 import junctions.JTAGIO
 import coreplex._
 
+/// Core with JTAG for debug only
+
 trait PeripheryJTAG extends TopNetwork {
   val module: PeripheryJTAGModule
   val coreplex: CoreplexRISCVPlatform
@@ -34,6 +36,8 @@ trait PeripheryJTAGModule extends TopNetworkModule {
   dtm.reset := io.jtag.TRST
 }
 
+/// Core with DTM for debug only
+
 trait PeripheryDTM extends TopNetwork {
   val module: PeripheryDTMModule
   val coreplex: CoreplexRISCVPlatform
@@ -52,6 +56,36 @@ trait PeripheryDTMModule extends TopNetworkModule {
   outer.coreplex.module.io.debug <> ToAsyncDebugBus(io.debug)
 }
 
+/// Core with DTM or JTAG based on a parameter
+
+trait PeripheryDebug extends TopNetwork {
+  val module: PeripheryDebugModule
+  val coreplex: CoreplexRISCVPlatform
+}
+
+trait PeripheryDebugBundle extends TopNetworkBundle {
+  val outer: PeripheryDebug
+
+  val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip)
+  val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip)
+}
+
+trait PeripheryDebugModule extends TopNetworkModule {
+  val outer: PeripheryDebug
+  val io: PeripheryDebugBundle
+
+  io.debug.foreach { dbg => outer.coreplex.module.io.debug <> ToAsyncDebugBus(dbg) }
+  io.jtag.foreach { jtag =>
+    val dtm = Module (new JtagDTMWithSync)
+    dtm.clock := jtag.TCK
+    dtm.reset := jtag.TRST
+    dtm.io.jtag <> jtag
+    outer.coreplex.module.io.debug <> dtm.io.debug
+  }
+}
+
+/// Real-time clock is based on RTCPeriod relative to Top clock
+
 trait PeripheryCounter extends TopNetwork {
   val module: PeripheryCounterModule
   val coreplex: CoreplexRISCVPlatform
@@ -75,6 +109,8 @@ trait PeripheryCounterModule extends TopNetworkModule {
   }
 }
 
+/// Coreplex will power-on running at 0x1000 (BootROM)
+
 trait HardwiredResetVector extends TopNetwork {
   val module: HardwiredResetVectorModule
   val coreplex: CoreplexRISCVPlatform