Fix Fragmenter to ensure logical operations must be sent out atomically.
Edited Fuzzer so that it can generate infinite operations when nOperations is net to 0
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@ -31,7 +31,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
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TransferSizes.none
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def mapManager(m: TLManagerParameters) = m.copy(
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supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
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supportsLogical = expandTransfer(m.supportsLogical),
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supportsLogical = shrinkTransfer(m.supportsLogical),
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supportsGet = expandTransfer(m.supportsGet),
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supportsPutFull = expandTransfer(m.supportsPutFull),
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supportsPutPartial = expandTransfer(m.supportsPutPartial),
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@ -108,9 +108,13 @@ class TLFuzzer(
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val dataBits = edge.bundle.dataBits
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// Progress through operations
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val num_reqs = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
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val num_resps = Reg(init = UInt(nOperations-1, log2Up(nOperations)))
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io.finished := num_resps === UInt(0)
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val num_reqs = Reg(init = UInt(nOperations, log2Up(nOperations)))
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val num_resps = Reg(init = UInt(nOperations, log2Up(nOperations)))
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if (nOperations>0) {
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io.finished := num_resps === UInt(0)
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} else {
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io.finished := Bool(false)
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}
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// Progress within each operation
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val a = out.a.bits
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@ -179,7 +183,11 @@ class TLFuzzer(
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UInt("b101") -> hbits))
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// Wire both the used and un-used channel signals
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out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
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if (nOperations>0) {
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out.a.valid := legal && alloc.valid && num_reqs =/= UInt(0)
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} else {
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out.a.valid := legal && alloc.valid
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}
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out.a.bits := bits
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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@ -190,12 +198,14 @@ class TLFuzzer(
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inc := !legal || req_done
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inc_beat := !legal || out.a.fire()
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when (out.a.fire() && a_last) {
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num_reqs := num_reqs - UInt(1)
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}
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if (nOperations>0) {
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when (out.a.fire() && a_last) {
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num_reqs := num_reqs - UInt(1)
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}
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when (out.d.fire() && d_last) {
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num_resps := num_resps - UInt(1)
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when (out.d.fire() && d_last) {
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num_resps := num_resps - UInt(1)
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}
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}
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}
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}
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