[Rocket] Send correct type for iomshr reqs
Also contain grow param bugfix
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32a1c27441
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9dd12545d0
@ -58,6 +58,8 @@ class WritebackReq(params: TLBundleParameters)(implicit p: Parameters) extends L
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val param = UInt(width = TLPermissions.cWidth)
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val way_en = Bits(width = nWays)
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val voluntary = Bool()
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override def cloneType = new WritebackReq(params)(p).asInstanceOf[this.type]
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}
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class IOMSHR(id: Int, edge: TLEdgeOut)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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@ -80,7 +82,7 @@ class IOMSHR(id: Int, edge: TLEdgeOut)(implicit p: Parameters) extends L1HellaCa
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val req_cmd_sc = req.cmd === M_XSC
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val grant_word = Reg(UInt(width = wordBits))
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val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(Bits(), 5)
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val s_idle :: s_mem_access :: s_mem_ack :: s_resp :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_idle)
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io.req.ready := (state === s_idle)
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@ -89,7 +91,7 @@ class IOMSHR(id: Int, edge: TLEdgeOut)(implicit p: Parameters) extends L1HellaCa
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val a_source = UInt(id)
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val a_address = req.addr
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val a_size = req.typ
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val a_size = storegen.size
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val a_data = Fill(beatWords, storegen.data)
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val get = edge.Get(a_source, a_address, a_size)._2
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@ -169,7 +171,6 @@ class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters)
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val s_invalid :: s_wb_req :: s_wb_resp :: s_meta_clear :: s_refill_req :: s_refill_resp :: s_meta_write_req :: s_meta_write_resp :: s_drain_rpq :: Nil = Enum(UInt(), 9)
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val state = Reg(init=s_invalid)
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val new_coh_state = Reg(init=ClientMetadata.onReset)
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val req = Reg(new MSHRReqInternal(cfg))
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val req_idx = req.addr(untagBits-1,blockOffBits)
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val req_tag = req.addr >> untagBits
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@ -196,11 +197,17 @@ class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters)
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rpq.io.enq.bits := io.req_bits
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rpq.io.deq.ready := (io.replay.ready && state === s_drain_rpq) || state === s_invalid
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// TODO clean all this coh state business up
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val new_coh_state = Reg(init=ClientMetadata.onReset)
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val grow_param = Reg(init=UInt(0))
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val coh_on_grant = Mux(dirties_coh,
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ClientMetadata.maximum,
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req.old_meta.coh.onGrant(req.cmd, io.mem_grant.bits.param))
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val (is_hit, grow_param, coh_on_hit) = io.req_bits.old_meta.coh.onAccess(io.req_bits.cmd)
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val (is_hit, missed_param, coh_on_hit) = io.req_bits.old_meta.coh.onAccess(io.req_bits.cmd)
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val (needs_wb, shrink_param, coh_on_wb) = io.req_bits.old_meta.coh.onCacheControl(M_FLUSH)
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val (hit_again, missed_again_param, _) = req.old_meta.coh.onCacheControl(io.req_bits.cmd)
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val (_, _, clear_coh_state) = req.old_meta.coh.onCacheControl(M_FLUSH)
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val (_, after_wb_param, _) = ClientMetadata.onReset.onAccess(req.cmd)
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when (state === s_drain_rpq && !rpq.io.deq.valid) {
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state := s_invalid
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@ -220,6 +227,7 @@ class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters)
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state := s_refill_resp
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}
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when (state === s_meta_clear && io.meta_write.ready) {
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grow_param := after_wb_param
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state := s_refill_req
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}
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when (state === s_wb_resp && io.mem_grant.valid) {
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@ -234,6 +242,7 @@ class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters)
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// going to ask for in s_refill_req
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when(cmd_requires_second_acquire) {
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req.cmd := io.req_bits.cmd
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when(!hit_again) { grow_param := missed_again_param }
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}
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dirties_coh := dirties_coh || isWrite(io.req_bits.cmd)
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}
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@ -246,6 +255,7 @@ class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters)
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new_coh_state := coh_on_hit
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}.otherwise { // upgrade permissions
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state := s_refill_req
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grow_param := missed_param
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}
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}.otherwise { // writback if necessary and refill
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state := Mux(needs_wb, s_wb_req, s_meta_clear)
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@ -274,9 +284,7 @@ class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters)
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io.meta_write.valid := state.isOneOf(s_meta_write_req, s_meta_clear)
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io.meta_write.bits.idx := req_idx
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io.meta_write.bits.data.coh := Mux(state === s_meta_clear,
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req.old_meta.coh.onCacheControl(M_FLUSH)._2,
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new_coh_state)
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io.meta_write.bits.data.coh := Mux(state === s_meta_clear, clear_coh_state, new_coh_state)
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io.meta_write.bits.data.tag := io.tag
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io.meta_write.bits.way_en := req.way_en
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@ -290,10 +298,10 @@ class MSHR(id: Int, edge: TLEdgeOut)(implicit cfg: DCacheConfig, p: Parameters)
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io.mem_acquire.valid := state === s_refill_req && grantackq.io.enq.ready
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io.mem_acquire.bits := edge.Acquire(
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fromSource = UInt(id),
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toAddress = Cat(io.tag, req_idx) << blockOffBits,
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lgSize = lgCacheBlockBytes,
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growPermissions = grow_param)._2
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fromSource = UInt(id),
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toAddress = Cat(io.tag, req_idx) << blockOffBits,
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lgSize = lgCacheBlockBytes,
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growPermissions = grow_param)._2
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io.meta_read.valid := state === s_drain_rpq
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io.meta_read.bits.idx := req_idx
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@ -796,7 +804,7 @@ class NonBlockingDCacheModule(outer: NonBlockingDCache)(implicit p: Parameters)
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val s2_tag_match_way = RegEnable(s1_tag_match_way, s1_clk_en)
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val s2_tag_match = s2_tag_match_way.orR
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val s2_hit_state = Mux1H(s2_tag_match_way, wayMap((w: Int) => RegEnable(meta.io.resp(w).coh, s1_clk_en)))
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val (s2_has_permission, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd)
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val (s2_has_permission, _, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd)
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val s2_hit = s2_tag_match && s2_has_permission && s2_hit_state === s2_new_hit_state
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// load-reserved/store-conditional
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