riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

CacheName no longer needed in RoCCInterface

Browse Source 
With dcacheParams passed to a RoCC, the CacheName no longer needs to be
specified.
This commit is contained in:
Schuyler Eldridge 2016-11-29 21:49:40 -05:00 committed by Henry Cook
parent 624db2034b
commit 36fe024671
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/rocket/rocc.scala
View File

@ -42,10 +42,10 @@ class RoCCResponse(implicit p: Parameters) extends CoreBundle()(p) {
class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
val cmd = Decoupled(new RoCCCommand).flip
val resp = Decoupled(new RoCCResponse)
val mem = new HellaCacheIO()(p.alterPartial({ case CacheName => CacheName("L1D") }))
val mem = new HellaCacheIO
val busy = Bool(OUTPUT)
val interrupt = Bool(OUTPUT)
// These should be handled differently, eventually
val autl = new ClientUncachedTileLinkIO
val utl = Vec(p(RoccNMemChannels), new ClientUncachedTileLinkIO)