commit
9433da8458
@ -38,32 +38,25 @@ case object IncludeJtagDTM extends Field[Boolean]
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*
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*/
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class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
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extends Module {
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class JtagDTMWithSync(implicit val p: Parameters) extends Module {
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// io.DebugBusIO <-> Sync <-> DebugBusIO <-> UInt <-> DTM Black Box
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val io = new Bundle {
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val jtag = new JTAGIO(true).flip
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val debug = new AsyncDebugBusIO
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}
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val req_width = io.debug.req.mem(0).getWidth
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val resp_width = io.debug.resp.mem(0).getWidth
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val jtag_dtm = Module (new DebugTransportModuleJtag(req_width, resp_width))
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val jtag_dtm = Module(new DebugTransportModuleJtag(req_width, resp_width))
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jtag_dtm.io.jtag <> io.jtag
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val dtm_req = Wire(new DecoupledIO(UInt(width = req_width)))
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val dtm_resp = Wire(new DecoupledIO(UInt(width = resp_width)))
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val io_debug_bus = Wire (new DebugBusIO)
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io.debug <> ToAsyncDebugBus(io_debug_bus)
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io.debug.req <> ToAsyncBundle(io_debug_bus.req)
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io_debug_bus.resp <> FromAsyncBundle(io.debug.resp)
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val dtm_req = jtag_dtm.io.dtm_req
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val dtm_resp = jtag_dtm.io.dtm_resp
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// Translate from straight 'bits' interface of the blackboxes
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// into the Resp/Req data structures.
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@ -74,20 +67,12 @@ class JtagDTMWithSync(depth: Int = 1, sync: Int = 3)(implicit val p: Parameters)
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dtm_resp.valid := io_debug_bus.resp.valid
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dtm_resp.bits := io_debug_bus.resp.bits.asUInt
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io_debug_bus.resp.ready := dtm_resp.ready
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dtm_req <> jtag_dtm.io.dtm_req
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jtag_dtm.io.dtm_resp <> dtm_resp
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}
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class DebugTransportModuleJtag(reqSize : Int, respSize : Int)(implicit val p: Parameters) extends BlackBox {
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val io = new Bundle {
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val jtag = new JTAGIO(true).flip()
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val dtm_req = new DecoupledIO(UInt(width = reqSize))
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val dtm_resp = new DecoupledIO(UInt(width = respSize)).flip()
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}
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}
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@ -9,8 +9,8 @@ final class AsyncBundle[T <: Data](val depth: Int, gen: T) extends Bundle
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{
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require (isPow2(depth))
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val mem = Vec(depth, gen)
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val ridx = UInt(width = log2Up(depth)+1).flip
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val widx = UInt(width = log2Up(depth)+1)
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val ridx = UInt(width = log2Ceil(depth)+1).flip
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val widx = UInt(width = log2Ceil(depth)+1)
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val ridx_valid = Bool().flip
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val widx_valid = Bool()
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val source_reset_n = Bool()
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