riscv/rocket-chip
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coreplex: rename RocketPlex => RocketTiles

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This commit is contained in:
Wesley W. Terpstra 2016-11-22 15:49:06 -08:00
parent bbabcf67ff
commit c230580157
2 changed files with 20 additions and 20 deletions
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12
src/main/scala/coreplex/Coreplex.scala
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@ -14,30 +14,30 @@ import rocket._
class DefaultCoreplex(implicit p: Parameters) extends BaseCoreplex
with CoreplexRISCVPlatform
with RocketPlex {
with RocketTiles {
override lazy val module = new DefaultCoreplexModule(this, () => new DefaultCoreplexBundle(this))
}
class DefaultCoreplexBundle[+L <: DefaultCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
with CoreplexRISCVPlatformBundle
with RocketPlexBundle
with RocketTilesBundle
class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with CoreplexRISCVPlatformModule
with RocketPlexModule
with RocketTilesModule
/////
class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex
with CoreplexRISCVPlatform
with AsyncRocketPlex {
with AsyncRocketTiles {
override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this))
}
class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer)
with CoreplexRISCVPlatformBundle
with AsyncRocketPlexBundle
with AsyncRocketTilesBundle
class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io)
with CoreplexRISCVPlatformModule
with AsyncRocketPlexModule
with AsyncRocketTilesModule

28
src/main/scala/coreplex/RocketPlex.scala → src/main/scala/coreplex/RocketTiles.scala
View File

@ -8,8 +8,8 @@ import uncore.coherence._
import rocket._
import uncore.devices.NTiles
trait RocketPlex extends CoreplexRISCVPlatform {
val module: RocketPlexModule
trait RocketTiles extends CoreplexRISCVPlatform {
val module: RocketTilesModule
val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new RocketTile(i)) }
val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
@ -22,13 +22,13 @@ trait RocketPlex extends CoreplexRISCVPlatform {
}
}
trait RocketPlexBundle extends CoreplexRISCVPlatformBundle {
val outer: CoreplexRISCVPlatform
trait RocketTilesBundle extends CoreplexRISCVPlatformBundle {
val outer: RocketTiles
}
trait RocketPlexModule extends CoreplexRISCVPlatformModule {
val outer: RocketPlex
val io: RocketPlexBundle
trait RocketTilesModule extends CoreplexRISCVPlatformModule {
val outer: RocketTiles
val io: RocketTilesBundle
outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
tile.io.hartid := UInt(i)
@ -67,8 +67,8 @@ class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
}
}
trait AsyncRocketPlex extends CoreplexRISCVPlatform {
val module: AsyncRocketPlexModule
trait AsyncRocketTiles extends CoreplexRISCVPlatform {
val module: AsyncRocketTilesModule
val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new AsyncRocketTile(i)) }
val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() }
@ -81,8 +81,8 @@ trait AsyncRocketPlex extends CoreplexRISCVPlatform {
}
}
trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle {
val outer: CoreplexRISCVPlatform
trait AsyncRocketTilesBundle extends CoreplexRISCVPlatformBundle {
val outer: AsyncRocketTiles
val tcrs = Vec(nTiles, new Bundle {
val clock = Clock(INPUT)
@ -90,9 +90,9 @@ trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle {
})
}
trait AsyncRocketPlexModule extends CoreplexRISCVPlatformModule {
val outer: AsyncRocketPlex
val io: AsyncRocketPlexBundle
trait AsyncRocketTilesModule extends CoreplexRISCVPlatformModule {
val outer: AsyncRocketTiles
val io: AsyncRocketTilesBundle
outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) =>
tile.clock := io.tcrs(i).clock