clint: undefined registers must be zero (#480)
This is needed so that SMP-safe boot loaders can safely read/write to the IPI register of non-existent harts.
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@ -84,7 +84,7 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
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/** Power, Reset, Clock, Interrupt */
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// Magic TL2 Incantation to create a TL2 Slave
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class CoreplexLocalInterrupter(address: BigInt = 0x02000000)(implicit val p: Parameters)
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extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
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extends TLRegisterRouter(address, size = ClintConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = true)(
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new TLRegBundle(p, _) with CoreplexLocalInterrupterBundle)(
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new TLRegModule(p, _, _) with CoreplexLocalInterrupterModule)
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{
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