riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

diplomacy: include InternalNodes for AXI4 and TL

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-11-23 18:53:03 -08:00
parent 9f1c668c4f
commit 30e890b480
2 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/main/scala/uncore/axi4/Nodes.scala
View File

@ -53,3 +53,6 @@ case class AXI4InputNode() extends InputNode(AXI4Imp)
// Nodes used for external ports
case class AXI4BlindOutputNode(portParams: AXI4SlavePortParameters) extends BlindOutputNode(AXI4Imp)(portParams)
case class AXI4BlindInputNode(portParams: AXI4MasterPortParameters) extends BlindInputNode(AXI4Imp)(portParams)
case class AXI4InternalOutputNode(portParams: AXI4SlavePortParameters) extends InternalOutputNode(AXI4Imp)(portParams)
case class AXI4InternalInputNode(portParams: AXI4MasterPortParameters) extends InternalInputNode(AXI4Imp)(portParams)

3
src/main/scala/uncore/tilelink2/Nodes.scala
View File

@ -126,6 +126,9 @@ case class TLInputNode() extends InputNode(TLImp)
case class TLBlindOutputNode(portParams: TLManagerPortParameters) extends BlindOutputNode(TLImp)(portParams)
case class TLBlindInputNode(portParams: TLClientPortParameters) extends BlindInputNode(TLImp)(portParams)
case class TLInternalOutputNode(portParams: TLManagerPortParameters) extends InternalOutputNode(TLImp)(portParams)
case class TLInternalInputNode(portParams: TLClientPortParameters) extends InternalInputNode(TLImp)(portParams)
/** Synthesizeable unit tests */
import unittest._