commit
549e006988
@ -61,7 +61,7 @@ endif
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ifeq ($(SUITE),GroundtestSuiteB)
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PROJECT=groundtest
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CONFIGS=BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
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ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig
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ComparatorConfig ComparatorBufferlessConfig ComparatorStatelessConfig
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endif
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ifeq ($(SUITE),UnittestSuite)
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@ -124,39 +124,39 @@ class WithNCores(n: Int) extends Config(
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class WithNBanksPerMemChannel(n: Int) extends Config(
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(pname, site, here, up) => pname match {
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case BankedL2Config => up(BankedL2Config).copy(nBanksPerChannel = n)
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case BankedL2Config => up(BankedL2Config, site).copy(nBanksPerChannel = n)
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case _ => throw new CDEMatchError
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})
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class WithNTrackersPerBank(n: Int) extends Config(
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(pname, site, here, up) => pname match {
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case BroadcastConfig => up(BroadcastConfig).copy(nTrackers = n)
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case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n)
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case _ => throw new CDEMatchError
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})
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// This is the number of sets **per way**
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class WithL1ICacheSets(sets: Int) extends Config(
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(pname, site, here, up) => pname match {
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case CacheName("L1I") => up(CacheName("L1I")).copy(nSets = sets)
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case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = sets)
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case _ => throw new CDEMatchError
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})
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// This is the number of sets **per way**
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class WithL1DCacheSets(sets: Int) extends Config(
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(pname, site, here, up) => pname match {
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case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = sets)
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = sets)
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case _ => throw new CDEMatchError
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})
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class WithL1ICacheWays(ways: Int) extends Config(
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(pname, site, here, up) => pname match {
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case CacheName("L1I") => up(CacheName("L1I")).copy(nWays = ways)
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case CacheName("L1I") => up(CacheName("L1I"), site).copy(nWays = ways)
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case _ => throw new CDEMatchError
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})
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class WithL1DCacheWays(ways: Int) extends Config(
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(pname, site, here, up) => pname match {
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case CacheName("L1D") => up(CacheName("L1D")).copy(nWays = ways)
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nWays = ways)
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case _ => throw new CDEMatchError
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})
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@ -169,7 +169,7 @@ class WithCacheBlockBytes(linesize: Int) extends Config(
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class WithDataScratchpad(n: Int) extends Config(
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(pname,site,here,up) => pname match {
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case DataScratchpadSize => n
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case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = n / site(CacheBlockBytes))
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = n / site(CacheBlockBytes))
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case _ => throw new CDEMatchError
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})
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@ -188,7 +188,7 @@ class WithL2Cache extends Config(
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class WithBufferlessBroadcastHub extends Config(
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(pname, site, here, up) => pname match {
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case BroadcastConfig => up(BroadcastConfig).copy(bufferless = true)
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case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true)
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})
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/**
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@ -206,12 +206,12 @@ class WithBufferlessBroadcastHub extends Config(
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class WithStatelessBridge extends Config(
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(pname,site,here,up) => pname match {
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/* !!! FIXME
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case BankedL2Config => up(BankedL2Config).copy(coherenceManager = { case (_, _) =>
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case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (_, _) =>
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val pass = LazyModule(new TLBuffer(0))
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(pass.node, pass.node)
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})
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*/
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case DCacheKey => up(DCacheKey).copy(nMSHRs = 0)
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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case _ => throw new CDEMatchError
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})
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@ -227,7 +227,7 @@ class WithL2Capacity(size_kb: Int) extends Config(
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class WithNL2Ways(n: Int) extends Config(
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(pname,site,here,up) => pname match {
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case CacheName("L2") => up(CacheName("L2")).copy(nWays = n)
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case CacheName("L2") => up(CacheName("L2"), site).copy(nWays = n)
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})
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class WithRV32 extends Config(
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@ -239,7 +239,7 @@ class WithRV32 extends Config(
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class WithBlockingL1 extends Config(
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(pname,site,here,up) => pname match {
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case DCacheKey => up(DCacheKey).copy(nMSHRs = 0)
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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case _ => throw new CDEMatchError
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})
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@ -250,9 +250,9 @@ class WithSmallCores extends Config(
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case UseVM => false
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case BtbKey => BtbParameters(nEntries = 0)
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case NAcquireTransactors => 2
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case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
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case CacheName("L1I") => up(CacheName("L1I")).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
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case DCacheKey => up(DCacheKey).copy(nMSHRs = 0)
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
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case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
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case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
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case _ => throw new CDEMatchError
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})
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@ -123,7 +123,7 @@ class WithAtomics extends Config(
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class WithPrefetches extends Config(
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(pname, site, here, up) => pname match {
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case ComparatorKey => up(ComparatorKey).copy(prefetches = true)
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case ComparatorKey => up(ComparatorKey, site).copy(prefetches = true)
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case _ => throw new CDEMatchError
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})
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@ -202,6 +202,6 @@ class WithTraceGen extends Config(
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}.flatten
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}
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case UseAtomics => true
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case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = 16, nWays = 1)
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case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 16, nWays = 1)
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case _ => throw new CDEMatchError
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})
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@ -28,8 +28,9 @@ class BasePlatformConfig extends Config(
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case PeripheryBusArithmetic => true
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// Note that PLIC asserts that this is > 0.
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case IncludeJtagDTM => false
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case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4)
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case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4)
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case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
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case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
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case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case _ => throw new CDEMatchError
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})
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@ -56,14 +57,14 @@ class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
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class WithNMemoryChannels(n: Int) extends Config(
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(pname,site,here,up) => pname match {
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case BankedL2Config => up(BankedL2Config).copy(nMemoryChannels = n)
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case BankedL2Config => up(BankedL2Config, site).copy(nMemoryChannels = n)
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case _ => throw new CDEMatchError
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}
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)
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class WithExtMemSize(n: Long) extends Config(
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(pname,site,here,up) => pname match {
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case ExtMem => up(ExtMem).copy(size = n)
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case ExtMem => up(ExtMem, site).copy(size = n)
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case _ => throw new CDEMatchError
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}
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)
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@ -94,7 +95,7 @@ class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
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class WithEdgeDataBits(dataBits: Int) extends Config(
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(pname, site, here, up) => pname match {
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case ExtMem => up(ExtMem).copy(beatBytes = dataBits/8)
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case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8)
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case _ => throw new CDEMatchError
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})
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@ -168,3 +169,9 @@ class WithNBreakpoints(hwbp: Int) extends Config (
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case _ => throw new CDEMatchError
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}
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)
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class WithRTCPeriod(nCycles: Int) extends Config(
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(pname, site, here) => pname match {
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case RTCPeriod => nCycles
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case _ => throw new CDEMatchError
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})
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|
@ -20,9 +20,11 @@ import scala.math.max
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import coreplex._
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/** Specifies the size of external memory */
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case class AXIMasterConfig(base: Long, size: Long, beatBytes: Int, idBits: Int)
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case object ExtMem extends Field[AXIMasterConfig]
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case object ExtBus extends Field[AXIMasterConfig]
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case class MasterConfig(base: Long, size: Long, beatBytes: Int, idBits: Int)
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case object ExtMem extends Field[MasterConfig]
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case object ExtBus extends Field[MasterConfig]
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case class SlaveConfig(beatBytes: Int, idBits: Int, sourceBits: Int)
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case object ExtIn extends Field[SlaveConfig]
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/** Specifies the number of external interrupts */
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case object NExtTopInterrupts extends Field[Int]
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/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
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@ -70,6 +72,14 @@ trait PeripheryExtInterruptsModule {
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/////
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trait PeripheryNoMem extends TopNetwork {
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private val channels = p(BankedL2Config).nMemoryChannels
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require (channels == 0)
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val mem = Seq()
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}
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/////
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trait PeripheryMasterAXI4Mem {
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this: TopNetwork =>
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val module: PeripheryMasterAXI4MemModule
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@ -155,14 +165,17 @@ trait PeripheryMasterAXI4MMIOModule {
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// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
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trait PeripherySlaveAXI4 extends L2Crossbar {
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||||
private val axiIdBits = 8
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private val tlIdBits = 2 // at most 4 AXI requets inflight at a time
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||||
|
||||
private val config = p(ExtIn)
|
||||
val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters(
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||||
masters = Seq(AXI4MasterParameters(
|
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id = IdRange(0, 1 << axiIdBits)))))
|
||||
id = IdRange(0, 1 << config.idBits)))))
|
||||
|
||||
l2.node := TLSourceShrinker(1 << tlIdBits)(AXI4ToTL()(AXI4Fragmenter()(l2_axi4)))
|
||||
l2.node :=
|
||||
TLSourceShrinker(1 << config.sourceBits)(
|
||||
TLWidthWidget(config.beatBytes)(
|
||||
AXI4ToTL()(
|
||||
AXI4Fragmenter()(
|
||||
l2_axi4))))
|
||||
}
|
||||
|
||||
trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle {
|
||||
@ -178,6 +191,69 @@ trait PeripherySlaveAXI4Module extends L2CrossbarModule {
|
||||
|
||||
/////
|
||||
|
||||
// Add an external TL-UL slave
|
||||
trait PeripheryMasterTLMMIO {
|
||||
this: TopNetwork =>
|
||||
|
||||
private val config = p(ExtBus)
|
||||
val mmio_tl = TLBlindOutputNode(TLManagerPortParameters(
|
||||
managers = Seq(TLManagerParameters(
|
||||
address = List(AddressSet(BigInt(config.base), config.size-1)),
|
||||
executable = true,
|
||||
supportsGet = TransferSizes(1, cacheBlockBytes),
|
||||
supportsPutFull = TransferSizes(1, cacheBlockBytes),
|
||||
supportsPutPartial = TransferSizes(1, cacheBlockBytes))),
|
||||
beatBytes = config.beatBytes))
|
||||
|
||||
mmio_tl :=
|
||||
TLSourceShrinker(config.idBits)(
|
||||
TLWidthWidget(socBusConfig.beatBytes)(
|
||||
socBus.node))
|
||||
}
|
||||
|
||||
trait PeripheryMasterTLMMIOBundle {
|
||||
this: TopNetworkBundle {
|
||||
val outer: PeripheryMasterTLMMIO
|
||||
} =>
|
||||
val mmio_tl = outer.mmio_tl.bundleOut
|
||||
}
|
||||
|
||||
trait PeripheryMasterTLMMIOModule {
|
||||
this: TopNetworkModule {
|
||||
val outer: PeripheryMasterTLMMIO
|
||||
val io: PeripheryMasterTLMMIOBundle
|
||||
} =>
|
||||
// nothing to do
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
// NOTE: this port is NOT allowed to issue Acquires
|
||||
trait PeripherySlaveTL extends L2Crossbar {
|
||||
private val config = p(ExtIn)
|
||||
val l2_tl = TLBlindInputNode(TLClientPortParameters(
|
||||
clients = Seq(TLClientParameters(
|
||||
sourceId = IdRange(0, 1 << config.idBits)))))
|
||||
|
||||
l2.node :=
|
||||
TLSourceShrinker(1 << config.sourceBits)(
|
||||
TLWidthWidget(config.beatBytes)(
|
||||
l2_tl))
|
||||
}
|
||||
|
||||
trait PeripherySlaveTLBundle extends L2CrossbarBundle {
|
||||
val outer: PeripherySlaveTL
|
||||
val l2_tl = outer.l2_tl.bundleIn
|
||||
}
|
||||
|
||||
trait PeripherySlaveTLModule extends L2CrossbarModule {
|
||||
val outer: PeripherySlaveTL
|
||||
val io: PeripherySlaveTLBundle
|
||||
// nothing to do
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait PeripheryBootROM {
|
||||
this: TopNetwork =>
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
|
@ -11,6 +11,8 @@ import util._
|
||||
import junctions.JTAGIO
|
||||
import coreplex._
|
||||
|
||||
/// Core with JTAG for debug only
|
||||
|
||||
trait PeripheryJTAG extends TopNetwork {
|
||||
val module: PeripheryJTAGModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
@ -34,6 +36,8 @@ trait PeripheryJTAGModule extends TopNetworkModule {
|
||||
dtm.reset := io.jtag.TRST
|
||||
}
|
||||
|
||||
/// Core with DTM for debug only
|
||||
|
||||
trait PeripheryDTM extends TopNetwork {
|
||||
val module: PeripheryDTMModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
@ -52,6 +56,36 @@ trait PeripheryDTMModule extends TopNetworkModule {
|
||||
outer.coreplex.module.io.debug <> ToAsyncDebugBus(io.debug)
|
||||
}
|
||||
|
||||
/// Core with DTM or JTAG based on a parameter
|
||||
|
||||
trait PeripheryDebug extends TopNetwork {
|
||||
val module: PeripheryDebugModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
}
|
||||
|
||||
trait PeripheryDebugBundle extends TopNetworkBundle {
|
||||
val outer: PeripheryDebug
|
||||
|
||||
val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip)
|
||||
val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip)
|
||||
}
|
||||
|
||||
trait PeripheryDebugModule extends TopNetworkModule {
|
||||
val outer: PeripheryDebug
|
||||
val io: PeripheryDebugBundle
|
||||
|
||||
io.debug.foreach { dbg => outer.coreplex.module.io.debug <> ToAsyncDebugBus(dbg) }
|
||||
io.jtag.foreach { jtag =>
|
||||
val dtm = Module (new JtagDTMWithSync)
|
||||
dtm.clock := jtag.TCK
|
||||
dtm.reset := jtag.TRST
|
||||
dtm.io.jtag <> jtag
|
||||
outer.coreplex.module.io.debug <> dtm.io.debug
|
||||
}
|
||||
}
|
||||
|
||||
/// Real-time clock is based on RTCPeriod relative to Top clock
|
||||
|
||||
trait PeripheryCounter extends TopNetwork {
|
||||
val module: PeripheryCounterModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
@ -75,6 +109,8 @@ trait PeripheryCounterModule extends TopNetworkModule {
|
||||
}
|
||||
}
|
||||
|
||||
/// Coreplex will power-on running at 0x1000 (BootROM)
|
||||
|
||||
trait HardwiredResetVector extends TopNetwork {
|
||||
val module: HardwiredResetVectorModule
|
||||
val coreplex: CoreplexRISCVPlatform
|
||||
|
@ -53,3 +53,6 @@ case class AXI4InputNode() extends InputNode(AXI4Imp)
|
||||
// Nodes used for external ports
|
||||
case class AXI4BlindOutputNode(portParams: AXI4SlavePortParameters) extends BlindOutputNode(AXI4Imp)(portParams)
|
||||
case class AXI4BlindInputNode(portParams: AXI4MasterPortParameters) extends BlindInputNode(AXI4Imp)(portParams)
|
||||
|
||||
case class AXI4InternalOutputNode(portParams: AXI4SlavePortParameters) extends InternalOutputNode(AXI4Imp)(portParams)
|
||||
case class AXI4InternalInputNode(portParams: AXI4MasterPortParameters) extends InternalInputNode(AXI4Imp)(portParams)
|
||||
|
@ -126,6 +126,9 @@ case class TLInputNode() extends InputNode(TLImp)
|
||||
case class TLBlindOutputNode(portParams: TLManagerPortParameters) extends BlindOutputNode(TLImp)(portParams)
|
||||
case class TLBlindInputNode(portParams: TLClientPortParameters) extends BlindInputNode(TLImp)(portParams)
|
||||
|
||||
case class TLInternalOutputNode(portParams: TLManagerPortParameters) extends InternalOutputNode(TLImp)(portParams)
|
||||
case class TLInternalInputNode(portParams: TLClientPortParameters) extends InternalInputNode(TLImp)(portParams)
|
||||
|
||||
/** Synthesizeable unit tests */
|
||||
import unittest._
|
||||
|
||||
|
@ -6,7 +6,8 @@ class CDEMatchError() extends Exception {
|
||||
}
|
||||
|
||||
abstract class View {
|
||||
final def apply[T](pname: Field[T]): T = find(pname, this).asInstanceOf[T]
|
||||
final def apply[T](pname: Field[T]): T = apply(pname, this)
|
||||
final def apply[T](pname: Field[T], site: View): T = find(pname, site).asInstanceOf[T]
|
||||
|
||||
protected[config] def find(pname: Any, site: View): Any
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user