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Merge pull request #451 from ucb-bar/more-configs

More configs
This commit is contained in:
Yunsup Lee 2016-11-24 09:44:52 -08:00 committed by GitHub
commit 549e006988
9 changed files with 158 additions and 32 deletions

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@ -61,7 +61,7 @@ endif
ifeq ($(SUITE),GroundtestSuiteB)
PROJECT=groundtest
CONFIGS=BroadcastRegressionTestConfig BufferlessRegressionTestConfig CacheRegressionTestConfig \
ComparatorConfig ComparatorBufferlessConfig ComparatorL2Config ComparatorStatelessConfig
ComparatorConfig ComparatorBufferlessConfig ComparatorStatelessConfig
endif
ifeq ($(SUITE),UnittestSuite)

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@ -124,39 +124,39 @@ class WithNCores(n: Int) extends Config(
class WithNBanksPerMemChannel(n: Int) extends Config(
(pname, site, here, up) => pname match {
case BankedL2Config => up(BankedL2Config).copy(nBanksPerChannel = n)
case BankedL2Config => up(BankedL2Config, site).copy(nBanksPerChannel = n)
case _ => throw new CDEMatchError
})
class WithNTrackersPerBank(n: Int) extends Config(
(pname, site, here, up) => pname match {
case BroadcastConfig => up(BroadcastConfig).copy(nTrackers = n)
case BroadcastConfig => up(BroadcastConfig, site).copy(nTrackers = n)
case _ => throw new CDEMatchError
})
// This is the number of sets **per way**
class WithL1ICacheSets(sets: Int) extends Config(
(pname, site, here, up) => pname match {
case CacheName("L1I") => up(CacheName("L1I")).copy(nSets = sets)
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = sets)
case _ => throw new CDEMatchError
})
// This is the number of sets **per way**
class WithL1DCacheSets(sets: Int) extends Config(
(pname, site, here, up) => pname match {
case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = sets)
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = sets)
case _ => throw new CDEMatchError
})
class WithL1ICacheWays(ways: Int) extends Config(
(pname, site, here, up) => pname match {
case CacheName("L1I") => up(CacheName("L1I")).copy(nWays = ways)
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nWays = ways)
case _ => throw new CDEMatchError
})
class WithL1DCacheWays(ways: Int) extends Config(
(pname, site, here, up) => pname match {
case CacheName("L1D") => up(CacheName("L1D")).copy(nWays = ways)
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nWays = ways)
case _ => throw new CDEMatchError
})
@ -169,7 +169,7 @@ class WithCacheBlockBytes(linesize: Int) extends Config(
class WithDataScratchpad(n: Int) extends Config(
(pname,site,here,up) => pname match {
case DataScratchpadSize => n
case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = n / site(CacheBlockBytes))
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = n / site(CacheBlockBytes))
case _ => throw new CDEMatchError
})
@ -188,7 +188,7 @@ class WithL2Cache extends Config(
class WithBufferlessBroadcastHub extends Config(
(pname, site, here, up) => pname match {
case BroadcastConfig => up(BroadcastConfig).copy(bufferless = true)
case BroadcastConfig => up(BroadcastConfig, site).copy(bufferless = true)
})
/**
@ -206,12 +206,12 @@ class WithBufferlessBroadcastHub extends Config(
class WithStatelessBridge extends Config(
(pname,site,here,up) => pname match {
/* !!! FIXME
case BankedL2Config => up(BankedL2Config).copy(coherenceManager = { case (_, _) =>
case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (_, _) =>
val pass = LazyModule(new TLBuffer(0))
(pass.node, pass.node)
})
*/
case DCacheKey => up(DCacheKey).copy(nMSHRs = 0)
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
case _ => throw new CDEMatchError
})
@ -227,7 +227,7 @@ class WithL2Capacity(size_kb: Int) extends Config(
class WithNL2Ways(n: Int) extends Config(
(pname,site,here,up) => pname match {
case CacheName("L2") => up(CacheName("L2")).copy(nWays = n)
case CacheName("L2") => up(CacheName("L2"), site).copy(nWays = n)
})
class WithRV32 extends Config(
@ -239,7 +239,7 @@ class WithRV32 extends Config(
class WithBlockingL1 extends Config(
(pname,site,here,up) => pname match {
case DCacheKey => up(DCacheKey).copy(nMSHRs = 0)
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
case _ => throw new CDEMatchError
})
@ -250,9 +250,9 @@ class WithSmallCores extends Config(
case UseVM => false
case BtbKey => BtbParameters(nEntries = 0)
case NAcquireTransactors => 2
case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
case CacheName("L1I") => up(CacheName("L1I")).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
case DCacheKey => up(DCacheKey).copy(nMSHRs = 0)
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
case CacheName("L1I") => up(CacheName("L1I"), site).copy(nSets = 64, nWays = 1, nTLBEntries = 4)
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
case _ => throw new CDEMatchError
})

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@ -123,7 +123,7 @@ class WithAtomics extends Config(
class WithPrefetches extends Config(
(pname, site, here, up) => pname match {
case ComparatorKey => up(ComparatorKey).copy(prefetches = true)
case ComparatorKey => up(ComparatorKey, site).copy(prefetches = true)
case _ => throw new CDEMatchError
})
@ -202,6 +202,6 @@ class WithTraceGen extends Config(
}.flatten
}
case UseAtomics => true
case CacheName("L1D") => up(CacheName("L1D")).copy(nSets = 16, nWays = 1)
case CacheName("L1D") => up(CacheName("L1D"), site).copy(nSets = 16, nWays = 1)
case _ => throw new CDEMatchError
})

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@ -28,8 +28,9 @@ class BasePlatformConfig extends Config(
case PeripheryBusArithmetic => true
// Note that PLIC asserts that this is > 0.
case IncludeJtagDTM => false
case ExtMem => AXIMasterConfig(0x80000000L, 0x10000000L, 8, 4)
case ExtBus => AXIMasterConfig(0x60000000L, 0x20000000L, 8, 4)
case ExtMem => MasterConfig(base=0x80000000L, size=0x10000000L, beatBytes=8, idBits=4)
case ExtBus => MasterConfig(base=0x60000000L, size=0x20000000L, beatBytes=8, idBits=4)
case ExtIn => SlaveConfig(beatBytes=8, idBits=8, sourceBits=2)
case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
case _ => throw new CDEMatchError
})
@ -56,14 +57,14 @@ class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
class WithNMemoryChannels(n: Int) extends Config(
(pname,site,here,up) => pname match {
case BankedL2Config => up(BankedL2Config).copy(nMemoryChannels = n)
case BankedL2Config => up(BankedL2Config, site).copy(nMemoryChannels = n)
case _ => throw new CDEMatchError
}
)
class WithExtMemSize(n: Long) extends Config(
(pname,site,here,up) => pname match {
case ExtMem => up(ExtMem).copy(size = n)
case ExtMem => up(ExtMem, site).copy(size = n)
case _ => throw new CDEMatchError
}
)
@ -94,7 +95,7 @@ class RoccExampleConfig extends Config(new WithRoccExample ++ new BaseConfig)
class WithEdgeDataBits(dataBits: Int) extends Config(
(pname, site, here, up) => pname match {
case ExtMem => up(ExtMem).copy(beatBytes = dataBits/8)
case ExtMem => up(ExtMem, site).copy(beatBytes = dataBits/8)
case _ => throw new CDEMatchError
})
@ -168,3 +169,9 @@ class WithNBreakpoints(hwbp: Int) extends Config (
case _ => throw new CDEMatchError
}
)
class WithRTCPeriod(nCycles: Int) extends Config(
(pname, site, here) => pname match {
case RTCPeriod => nCycles
case _ => throw new CDEMatchError
})

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@ -20,9 +20,11 @@ import scala.math.max
import coreplex._
/** Specifies the size of external memory */
case class AXIMasterConfig(base: Long, size: Long, beatBytes: Int, idBits: Int)
case object ExtMem extends Field[AXIMasterConfig]
case object ExtBus extends Field[AXIMasterConfig]
case class MasterConfig(base: Long, size: Long, beatBytes: Int, idBits: Int)
case object ExtMem extends Field[MasterConfig]
case object ExtBus extends Field[MasterConfig]
case class SlaveConfig(beatBytes: Int, idBits: Int, sourceBits: Int)
case object ExtIn extends Field[SlaveConfig]
/** Specifies the number of external interrupts */
case object NExtTopInterrupts extends Field[Int]
/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
@ -70,6 +72,14 @@ trait PeripheryExtInterruptsModule {
/////
trait PeripheryNoMem extends TopNetwork {
private val channels = p(BankedL2Config).nMemoryChannels
require (channels == 0)
val mem = Seq()
}
/////
trait PeripheryMasterAXI4Mem {
this: TopNetwork =>
val module: PeripheryMasterAXI4MemModule
@ -155,14 +165,17 @@ trait PeripheryMasterAXI4MMIOModule {
// PeripherySlaveAXI4 is an example, make your own cake pattern like this one.
trait PeripherySlaveAXI4 extends L2Crossbar {
private val axiIdBits = 8
private val tlIdBits = 2 // at most 4 AXI requets inflight at a time
private val config = p(ExtIn)
val l2_axi4 = AXI4BlindInputNode(AXI4MasterPortParameters(
masters = Seq(AXI4MasterParameters(
id = IdRange(0, 1 << axiIdBits)))))
id = IdRange(0, 1 << config.idBits)))))
l2.node := TLSourceShrinker(1 << tlIdBits)(AXI4ToTL()(AXI4Fragmenter()(l2_axi4)))
l2.node :=
TLSourceShrinker(1 << config.sourceBits)(
TLWidthWidget(config.beatBytes)(
AXI4ToTL()(
AXI4Fragmenter()(
l2_axi4))))
}
trait PeripherySlaveAXI4Bundle extends L2CrossbarBundle {
@ -178,6 +191,69 @@ trait PeripherySlaveAXI4Module extends L2CrossbarModule {
/////
// Add an external TL-UL slave
trait PeripheryMasterTLMMIO {
this: TopNetwork =>
private val config = p(ExtBus)
val mmio_tl = TLBlindOutputNode(TLManagerPortParameters(
managers = Seq(TLManagerParameters(
address = List(AddressSet(BigInt(config.base), config.size-1)),
executable = true,
supportsGet = TransferSizes(1, cacheBlockBytes),
supportsPutFull = TransferSizes(1, cacheBlockBytes),
supportsPutPartial = TransferSizes(1, cacheBlockBytes))),
beatBytes = config.beatBytes))
mmio_tl :=
TLSourceShrinker(config.idBits)(
TLWidthWidget(socBusConfig.beatBytes)(
socBus.node))
}
trait PeripheryMasterTLMMIOBundle {
this: TopNetworkBundle {
val outer: PeripheryMasterTLMMIO
} =>
val mmio_tl = outer.mmio_tl.bundleOut
}
trait PeripheryMasterTLMMIOModule {
this: TopNetworkModule {
val outer: PeripheryMasterTLMMIO
val io: PeripheryMasterTLMMIOBundle
} =>
// nothing to do
}
/////
// NOTE: this port is NOT allowed to issue Acquires
trait PeripherySlaveTL extends L2Crossbar {
private val config = p(ExtIn)
val l2_tl = TLBlindInputNode(TLClientPortParameters(
clients = Seq(TLClientParameters(
sourceId = IdRange(0, 1 << config.idBits)))))
l2.node :=
TLSourceShrinker(1 << config.sourceBits)(
TLWidthWidget(config.beatBytes)(
l2_tl))
}
trait PeripherySlaveTLBundle extends L2CrossbarBundle {
val outer: PeripherySlaveTL
val l2_tl = outer.l2_tl.bundleIn
}
trait PeripherySlaveTLModule extends L2CrossbarModule {
val outer: PeripherySlaveTL
val io: PeripherySlaveTLBundle
// nothing to do
}
/////
trait PeripheryBootROM {
this: TopNetwork =>
val coreplex: CoreplexRISCVPlatform

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@ -11,6 +11,8 @@ import util._
import junctions.JTAGIO
import coreplex._
/// Core with JTAG for debug only
trait PeripheryJTAG extends TopNetwork {
val module: PeripheryJTAGModule
val coreplex: CoreplexRISCVPlatform
@ -34,6 +36,8 @@ trait PeripheryJTAGModule extends TopNetworkModule {
dtm.reset := io.jtag.TRST
}
/// Core with DTM for debug only
trait PeripheryDTM extends TopNetwork {
val module: PeripheryDTMModule
val coreplex: CoreplexRISCVPlatform
@ -52,6 +56,36 @@ trait PeripheryDTMModule extends TopNetworkModule {
outer.coreplex.module.io.debug <> ToAsyncDebugBus(io.debug)
}
/// Core with DTM or JTAG based on a parameter
trait PeripheryDebug extends TopNetwork {
val module: PeripheryDebugModule
val coreplex: CoreplexRISCVPlatform
}
trait PeripheryDebugBundle extends TopNetworkBundle {
val outer: PeripheryDebug
val debug = (!p(IncludeJtagDTM)).option(new DebugBusIO().flip)
val jtag = (p(IncludeJtagDTM)).option(new JTAGIO(true).flip)
}
trait PeripheryDebugModule extends TopNetworkModule {
val outer: PeripheryDebug
val io: PeripheryDebugBundle
io.debug.foreach { dbg => outer.coreplex.module.io.debug <> ToAsyncDebugBus(dbg) }
io.jtag.foreach { jtag =>
val dtm = Module (new JtagDTMWithSync)
dtm.clock := jtag.TCK
dtm.reset := jtag.TRST
dtm.io.jtag <> jtag
outer.coreplex.module.io.debug <> dtm.io.debug
}
}
/// Real-time clock is based on RTCPeriod relative to Top clock
trait PeripheryCounter extends TopNetwork {
val module: PeripheryCounterModule
val coreplex: CoreplexRISCVPlatform
@ -75,6 +109,8 @@ trait PeripheryCounterModule extends TopNetworkModule {
}
}
/// Coreplex will power-on running at 0x1000 (BootROM)
trait HardwiredResetVector extends TopNetwork {
val module: HardwiredResetVectorModule
val coreplex: CoreplexRISCVPlatform

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@ -53,3 +53,6 @@ case class AXI4InputNode() extends InputNode(AXI4Imp)
// Nodes used for external ports
case class AXI4BlindOutputNode(portParams: AXI4SlavePortParameters) extends BlindOutputNode(AXI4Imp)(portParams)
case class AXI4BlindInputNode(portParams: AXI4MasterPortParameters) extends BlindInputNode(AXI4Imp)(portParams)
case class AXI4InternalOutputNode(portParams: AXI4SlavePortParameters) extends InternalOutputNode(AXI4Imp)(portParams)
case class AXI4InternalInputNode(portParams: AXI4MasterPortParameters) extends InternalInputNode(AXI4Imp)(portParams)

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@ -126,6 +126,9 @@ case class TLInputNode() extends InputNode(TLImp)
case class TLBlindOutputNode(portParams: TLManagerPortParameters) extends BlindOutputNode(TLImp)(portParams)
case class TLBlindInputNode(portParams: TLClientPortParameters) extends BlindInputNode(TLImp)(portParams)
case class TLInternalOutputNode(portParams: TLManagerPortParameters) extends InternalOutputNode(TLImp)(portParams)
case class TLInternalInputNode(portParams: TLClientPortParameters) extends InternalInputNode(TLImp)(portParams)
/** Synthesizeable unit tests */
import unittest._

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@ -6,7 +6,8 @@ class CDEMatchError() extends Exception {
}
abstract class View {
final def apply[T](pname: Field[T]): T = find(pname, this).asInstanceOf[T]
final def apply[T](pname: Field[T]): T = apply(pname, this)
final def apply[T](pname: Field[T], site: View): T = find(pname, site).asInstanceOf[T]
protected[config] def find(pname: Any, site: View): Any
}