Sagar Karandikar
83c6c2c9e2
rename refs to zynq-fpga to fpga-zynq
2014-08-29 10:26:48 -07:00
Henry Cook
78ab83d224
refactor fpga top/config
2014-08-28 13:07:54 -07:00
Scott Beamer
83380053de
use fpga backend for fpga
2014-08-26 15:56:27 -07:00
Henry Cook
bf356b9cb4
Refactor to combine fpga and vlsi tops, part 1
2014-08-24 19:30:53 -07:00
Henry Cook
17b2359c9a
htif parameters trait
2014-08-24 19:27:58 -07:00
Henry Cook
a41d55b643
Final parameter refactor.
2014-08-23 01:26:03 -07:00
Henry Cook
dc5643b12f
Final parameter refactor.
2014-08-23 01:19:36 -07:00
Scott Beamer
63b62394d9
added l2 to fpga
...
with new chisel & uncore, it goes into brams
2014-08-20 15:41:07 -07:00
Scott Beamer
e384b33cc3
don't generate a write mask for BigMem if it isn't used
...
not needed for llc data
2014-08-19 15:50:20 -07:00
Henry Cook
9b36162b67
Point rocket/ to rocket-staging repo
2014-08-19 14:20:15 -07:00
Henry Cook
2741bbf2b9
Point rocket/ to rocket-staging repo
2014-08-19 13:53:24 -07:00
Henry Cook
6a4193cf90
minor cache param cleanup
2014-08-19 11:38:46 -07:00
Henry Cook
2de268b3b1
Cache utility traits. Completely compiles, asm tests hang.
2014-08-19 11:38:20 -07:00
Henry Cook
ca5f38ff26
a few more fixes. some param lookups fail (here() in Alter blocks)
2014-08-19 11:38:11 -07:00
Henry Cook
0dac9a7467
Full conversion to params. Compiles but does not elaborate.
2014-08-19 11:38:02 -07:00
Adam Izraelevitz
4e6d69892d
Added initial brainstorm for parameter hierarchical flattening, does not compile ;)
2014-08-19 11:37:50 -07:00
Adam Izraelevitz
812353bace
Ported FPU parameters to new Chisel Parameters
2014-08-19 11:37:27 -07:00
Yunsup Lee
4ac8e59b1f
add .gitignore
2014-08-18 19:27:50 -07:00
Yunsup Lee
d520846638
add README and sbt files
2014-08-18 19:23:10 -07:00
Scott Beamer
e1a4d12c65
fix small typos in README
2014-08-14 17:59:24 -07:00
Henry Cook
1563c1bb36
Fixed cache params. Asm and bmark tests pass.
2014-08-12 15:00:54 -07:00
Henry Cook
e26f8a6f6a
Fix errors in derived cache params
2014-08-12 14:55:44 -07:00
Henry Cook
910c886837
bump chisel
2014-08-12 14:53:19 -07:00
Henry Cook
74796868e7
chisel bump
2014-08-12 10:58:09 -07:00
Henry Cook
0ca24a5d91
fix debug flags
2014-08-12 10:35:39 -07:00
Henry Cook
7f07771600
Cache utility traits. Completely compiles, asm tests hang.
2014-08-11 18:37:10 -07:00
Henry Cook
9ab3a4262c
Cache utility traits. Completely compiles, asm tests hang.
2014-08-11 18:35:49 -07:00
Henry Cook
1983260e6f
a few more fixes. some param lookups fail (here() in Alter blocks)
2014-08-10 23:08:21 -07:00
Henry Cook
63bd0b9d2a
Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
2014-08-08 12:27:47 -07:00
Henry Cook
f411fdcce3
Full conversion to params. Compiles but does not elaborate.
2014-08-08 12:21:57 -07:00
Scott Beamer
d3a8a224fe
README updated for new fpga flow
2014-08-07 14:52:56 -07:00
Scott Beamer
e390eba8ce
convert README to markdown
2014-08-07 14:50:31 -07:00
Scott Beamer
4109d7cc87
newest version of chisel needed for brams
2014-08-07 13:49:31 -07:00
Palmer Dabbelt
0fc3acb978
Update the directions on how to update Chisel
...
It seems that the update process in the README is really out of date
(it refers to scala-2.8 and chisel-1.1). I've updated it to what I
believe to be correct, which now just consists of pulling the Chisel
submodule.
Note that I tried this myself, but when I did it I also ran an "sbt
package" in the Chisel submodule top-level directory (there's no "sbt"
directory in there any more). I believe it's not necessary to run
"sbt package", but I really know nothing about SBT...
2014-08-05 11:56:03 -07:00
Palmer Dabbelt
693489da87
Add a note to the README about "make emulator-debug"
...
I made a clean checkout of reference-chip yesterday and wasn't able to
build the debug emulator without first having built the non-debug
emulator. I just added a note to the README to say this.
2014-08-05 11:53:55 -07:00
Adam Izraelevitz
08d81d0892
First cut at using new chisel parameters for toplevel parameters and fpu
2014-08-01 18:09:37 -07:00
Adam Izraelevitz
fcd68364ff
Merge branch 'master' of github.com:ucb-bar/reference-chip into dse
...
Conflicts:
src/main/scala/ReferenceChip.scala
2014-08-01 18:07:22 -07:00
Andrew Waterman
7bffc6c586
rename Unsigned.size to Unsigned.clog2
2014-06-14 13:58:07 -07:00
Andrew Waterman
3828c628c3
Remove vestigial control signals
2014-06-14 13:58:07 -07:00
Andrew Waterman
04593d433e
clean up Int <-> Boolean conversion stuff
2014-06-14 13:58:07 -07:00
Andrew Waterman
ac88ded35a
Use ROMs to reduce node count and improve QoR a bit
2014-06-14 13:58:07 -07:00
Andrew Waterman
88899eafe0
Reduce node count a bit
2014-06-14 13:58:07 -07:00
Jim Lawson
0c93567dea
Replace needWidth() with getWidth.
2014-06-13 14:58:52 -07:00
Jim Lawson
0020ded367
Replace needWidth() with getWidth.
2014-06-13 14:53:48 -07:00
Jim Lawson
de32595fba
Quick change to work with new Width class.
2014-06-13 12:00:50 -07:00
Jim Lawson
a04ef4f5f4
Quick change to work with new Width class.
...
Replace .width with .needWidth()
2014-06-13 11:44:43 -07:00
Andrew Waterman
1ae7a9376c
Fix unhandled LLC writeback hazard
2014-06-13 03:25:52 -07:00
Henry Cook
434da22283
Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
2014-05-28 17:16:49 -07:00
Henry Cook
dab675b231
refactor Metadata, clean and expand coherence API
2014-05-28 16:05:48 -07:00
Henry Cook
b0ccb88982
make outer cache type choice a top-level const
2014-05-28 14:46:07 -07:00
