Howard Mao
d0a14c6de9
separate TileLink converter/wrapper/unwrapper/narrower into separate file
2016-01-11 16:14:56 -08:00
Colin Schmidt
8d1afa4197
bump fpga repo
2016-01-09 17:50:29 -08:00
Howard Mao
806e40d19b
implement DMA streaming functionality
2016-01-07 19:26:15 -08:00
Howard Mao
9d2637c2c7
support empty submaps in interconnect generator
2016-01-07 11:55:24 -08:00
Howard Mao
80d97d5f9e
test DMA streaming
2016-01-06 21:38:12 -08:00
Howard Mao
46069ea13b
implement streaming DMA functionality
2016-01-06 21:37:56 -08:00
Howard Mao
05b359d357
support streaming DMA in DMA frontend
2016-01-06 18:17:41 -08:00
Howard Mao
673f73b051
add support for AXI streaming protocol
2016-01-05 20:04:49 -08:00
Howard Mao
2f71a3da5a
bump up submodule commits to merge commits
...
Github's PR system doesn't work so well with submodules, since it always
creates merge commits. We should probably avoid using it in the future.
2015-12-22 08:09:24 -08:00
Howard Mao
0f51ca4c10
Merge pull request #35 from ucb-bar/dma
...
Implement DMA unit
2015-12-22 10:33:59 -05:00
Howard Mao
b8d0376d3f
Merge pull request #1 from ucb-bar/dma
...
add DMA test
2015-12-22 10:33:48 -05:00
Howard Mao
dbe68056d9
Merge pull request #21 from ucb-bar/dma
...
Implement client-side DMA controller
2015-12-22 10:33:28 -05:00
Henry Cook
09f3c5a6e3
Merge pull request #6 from ucb-bar/dma
...
Implement DMA engine
2015-12-21 13:54:38 -08:00
Howard Mao
8190bf6e18
implement DMA unit
2015-12-16 21:27:48 -08:00
Howard Mao
872b162e1b
implement DMA engine
2015-12-16 21:27:31 -08:00
Howard Mao
24eecee148
add DMA test
2015-12-16 21:26:22 -08:00
Howard Mao
304d8b814a
Implement client-side DMA controller
2015-12-16 21:24:24 -08:00
Howard Mao
8a61177224
generalize TwoWayCounter
2015-12-16 21:07:30 -08:00
Howard Mao
1a272677ca
more fixes to L2 cache
2015-12-16 21:06:39 -08:00
Howard Mao
4858ca9a60
add a regression to test proper writeback
2015-12-16 21:05:56 -08:00
Howard Mao
a48237f36d
get rid of the rest of the PutBlock special casing in L2
2015-12-16 20:56:29 -08:00
Albert Magyar
01a3447989
Remove duplicate PseudoLRU class from rocket TLB
2015-12-16 16:12:47 -08:00
Howard Mao
560fdc19a8
add PLRU replacement option to L2 cache
2015-12-16 10:24:57 -08:00
Albert Magyar
922b1adc9c
Add optional PLRU replacement to the L2
2015-12-16 10:00:56 -08:00
Howard Mao
7ad9deeaee
Fix issues with request merging in L2 cache and add regression tests
...
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
2015-12-15 23:02:15 -08:00
Howard Mao
176d3c890c
add some more regression tests
2015-12-15 23:00:17 -08:00
Howard Mao
ddc79674f9
fix some issues with cache request merging
2015-12-15 21:31:02 -08:00
Colin Schmidt
c080e82e92
Merge pull request #34 from seldridge/rocketchip-addons-build
...
build.scala uses space-delimited ROCKETCHIP_ADDONS
2015-12-09 11:57:19 -08:00
Schuyler Eldridge
e50e4d4c84
build.scala uses space-delimited ROCKETCHIP_ADDONS
2015-12-09 14:17:16 -05:00
Andrew Waterman
91be080526
Merge pull request #32 from ucb-bar/javamaxpermsize
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Double Java MaxPermSize.
2015-12-07 13:58:41 -08:00
Jim Lawson
c5e9558571
Double Java MaxPermSize.
2015-12-07 12:05:06 -08:00
Howard Mao
0c91e00676
move GroundTest configs to a separate file
2015-12-06 03:01:05 -08:00
Howard Mao
e71293e2ae
fix bug in narrower logic
2015-12-06 02:58:12 -08:00
Howard Mao
484e8ce20b
add regression tests for catching specific memory bugs
2015-12-06 02:57:45 -08:00
Howard Mao
4f5dabcda2
add SCR file to device tree
2015-12-05 00:28:58 -08:00
Howard Mao
c57639b23f
reverse order of RWX bits for compatibility
2015-12-05 00:27:24 -08:00
Howard Mao
6fc1e92708
add option to print cycle count regardless of exit status
2015-12-04 12:04:13 -08:00
Sagar Karandikar
93aa370b87
yunsup's fix for dgemm-opt assertion failure
2015-12-03 14:03:10 -08:00
Howard Mao
f35b83d3ca
allow configuration of rocket ICache buffering
2015-12-02 17:18:39 -08:00
Howard Mao
7690de07e1
allow icache to configure which side of the way mux gets buffered
2015-12-02 17:17:49 -08:00
Howard Mao
369ee74a2c
change names of RoCC tilelink interfaces to be more sensible
2015-12-02 16:28:23 -08:00
Howard Mao
ebf2417a32
rocc-fpu-port merged into master for rocket
2015-12-02 09:02:43 -08:00
Howard Mao
f67b02fadb
Merge branch 'rocc-fpu-port'
2015-12-02 08:52:15 -08:00
Howard Mao
73b0263663
disconnect fpu port if no fpu-using RoCC accelerators
2015-12-01 20:41:58 -08:00
Howard Mao
3f8f726296
make rocc build independent from parameter structure
2015-12-01 18:47:52 -08:00
Howard Mao
dcca0b1d86
fix up FPU connection
2015-12-01 18:14:58 -08:00
Howard Mao
08f77ca90d
Merge branch 'master' into rocc-fpu-port
2015-12-01 18:00:28 -08:00
Howard Mao
cdc476a370
change Rocc parameterization
2015-12-01 17:56:09 -08:00
Howard Mao
e76dfa55f7
change the way rocc is parameterized
2015-12-01 17:54:56 -08:00
Andrew Waterman
e0d849fec5
Fix zscale testing
...
Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
