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Author SHA1 Message Date
Jacob Chang
ec3789b365
Add Cross Cover Property Library (#1149) 
Add cover points related to memory error to I/D Cache
 2017-12-07 18:46:10 -08:00
Andrew Waterman
5c204f98d5
When writing full words to ITIM, ECC errors are correctable (#1148) 
* When writing full words to ITIM, ECC errors are correctable

* Disable D$ tag reset state machine when using scratchpad
 2017-12-07 16:00:26 -08:00
Richard Xia
cfa819fc58
Merge pull request #1142 from freechipsproject/fix-typo-in-cover-property-name 
Fix typo in breakpoint cover property.
 2017-12-04 15:10:05 -08:00
Richard Xia
50de991f18 Fix typo in breakpoint cover property. 2017-12-04 14:04:24 -08:00
Wesley W. Terpstra
b8098d18be
diplomacy: remove the :=? operator in favour of magic :*=* (#1139) 
The reason for the :=? operator was for when you have an adapter chain
whose direction of cardinality you could not know. We used explicit
directives to tell these compositions which way to go.

Unfortunately, that makes the API leaky. You think the chain of adapters
is just one adapter, but you have to use strange Cardinality scopes to
use it. That's just bad.

The new :*=* just automagically figures it out from the graph.
 2017-12-01 18:28:37 -08:00
Wesley W. Terpstra
dedf396915
groundtest: connect the ibus to a fictitious master (#1140) 2017-12-01 18:28:24 -08:00
Henry Cook
71ddd797bf
Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i 
Added coverage point to cover the case when ECC error happens during …
 2017-12-01 18:00:11 -08:00
Gleb Gagarin
7c2df9f0bf Cover the case when there is an ECC error in DCache data array during fence.i execution 2017-12-01 16:28:28 -08:00
Gleb Gagarin
74bd61c556 Added coverage point to cover the case when ECC error happens during fence.i execution 2017-12-01 15:50:31 -08:00
Wesley W. Terpstra
4bac8be483
Merge pull request #1094 from freechipsproject/in-situ-unit-tests 
In situ unit tests
 2017-12-01 13:27:30 -08:00
Wesley W. Terpstra
8781d2b2e7 diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
Wesley W. Terpstra
a3e44375c6 ValName: 'lazy val' now also counts for providing a name 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
fe8d557751 PeripheryBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
93c8010aca FrontBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
e489c4226e diplomacy: remove node arity and allow empty Nexus nodes (Xbars) 
This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.

val x = TLXbar()
x := master
slave := x

val y = TLXbar()
x :=* y // only connect y if it gets used

This will create crossbar x, but crossbar y will disappear.
 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
6a25a3b7ac tilelink: we can have helper objects for terminal nodes now too! 
The new rule is you should have an object.apply method if you only have a
single .node.
 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
2092cb4ec8 diplomacy: reprotect Node bundles after module construction is completed 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
fdeed7bbb3 unittest: add an API for describing LazyModule unit tests 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
cc789e9063 diplomacy: protect more of the unstable API 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
8ed9e78903 diplomacy: support cloning of LazyModules 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
b43bcdfcd1 CloneModule: beat chisel into submission 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
1f23f9f865 diplomacy: categorize parameter resolution by direction+side 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
fbbfc9c096 diplomacy: include edge type in inward/outward node handles 
This is necessary capture the node implementation in the handle,
which is in turn necessary to support cloning a Node.
 2017-12-01 11:26:58 -08:00
Wesley W. Terpstra
ea03f71f97
Merge pull request #1135 from freechipsproject/decoupled-loop-fix 
TileLink compliance: d_bits may not depend on d_ready
 2017-11-30 18:21:37 -08:00
Wesley W. Terpstra
35506279af regmapper: fix d_ready => d_bits loop in RegField.bytes 
RegField.bytes updates only those bytes which are written every cycle.
However, there was a bug that it would try to return the updated value on reads.
This led to another TL-spec violating combinational path, just like the Debug module.
 2017-11-30 16:38:45 -08:00
Wesley W. Terpstra
fc1f5be316 Debug: fix a latent combinational loop (d_ready => d_bits) 
When passed a Wire, WNotify outputs that wire on reads wire => d_bits.
Furthermore, it updates the Wire when a write occures d_ready => wire.

These registers should be returning undefined value on read, anyway.
 2017-11-30 16:36:45 -08:00
Richard Xia
a447343074
Merge pull request #1129 from freechipsproject/add-exception-cover-properties 
Add cover properties for exceptions in the core.
 2017-11-30 16:23:14 -08:00
Richard Xia
4bd9c477ea Add cover properties for ECALL exceptions. 2017-11-30 14:27:04 -08:00
Richard Xia
29c70501f2 Add cover properties for exceptions in the core. 2017-11-30 14:27:04 -08:00
Henry Cook
bab0b99d7a
Merge pull request #1131 from freechipsproject/fix-dcache-tag-ecc-error-under-flush 
Avoid data corruption under correctable tag error during flush
 2017-11-30 12:27:15 -08:00
Andrew Waterman
890528c641 Avoid data corruption under correctable tag error during flush 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 16:09:44 -08:00
Andrew Waterman
34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)" 
This reverts commit 44eb4d12b5.
 2017-11-29 16:09:30 -08:00
Andrew Waterman
44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130) 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 09:42:00 -08:00
Megan Wachs
9d489c6dcd
Merge pull request #1128 from freechipsproject/chisel_527_fixed 
debug: Remove workaround for Chisel 3 #527
 2017-11-27 16:53:02 -08:00
Megan Wachs
f554ad7e2c debug: Remove workaround for Chisel 3 #527 2017-11-27 10:50:15 -08:00
Andrew Waterman
5155eb6059
Don't emit writeback state machine logic for scratchpad (#1127) 
Firrtl can't DCE it because it would require analyzing the state machine.
 2017-11-22 18:40:02 -06:00
Wesley W. Terpstra
a8d573beeb
Merge pull request #1123 from freechipsproject/dts-global 
DTS global
 2017-11-20 19:09:03 -08:00
Wesley W. Terpstra
6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores 
Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.

timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
 2017-11-20 18:09:57 -08:00
Wesley W. Terpstra
3b299397db diplomacy: bind resources to outer-most binding 
This is probably the wrong thing to do, but it is expedient for now.
We need a better way to do cross-coreplex visibility.
 2017-11-20 17:42:08 -08:00
Wesley W. Terpstra
44f99cd9a5 diplomacy: eliminate redundant bindings 2017-11-20 17:42:08 -08:00
Wesley W. Terpstra
baa31edf7d RocketTile: if the dcache is incoherent, report it in DTS 2017-11-20 17:42:06 -08:00
Andrew Waterman
39f1acfd34
Merge pull request #1122 from freechipsproject/fix-itim 
Fix ITIM deallocation during I$ refill causing data corruption
 2017-11-20 15:08:25 -08:00
Yunsup Lee
a60d7d419d icache: add a couple cover points for I$ and ITIM iteraction 2017-11-20 13:14:38 -08:00
Andrew Waterman
5e94884f09 Fix ITIM deallocation during I$ refill causing data corruption 
Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.

The workaround described in commit 3db066303b
still suffices, provided only the hart that owns the ITIM changes the ITIM
allocation.

This subsumes commit 3db066303b.
 2017-11-20 12:30:40 -08:00
Andrew Waterman
66b7a8a5ed Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM (#1079)" 
This reverts commit 3db066303b.
 2017-11-20 12:26:04 -08:00
Wesley W. Terpstra
342dd82fcf
Merge pull request #1119 from freechipsproject/verify-blocker-width 
Verify blocker width
 2017-11-18 15:45:24 -08:00
Wesley W. Terpstra
ec809483b0 BusBypass: assert fail if the widths of the two slaves do not match 2017-11-18 14:37:27 -08:00
Wesley W. Terpstra
c475c78c2f BusBlocker: don't provide an (incorrect) default value for width 2017-11-18 14:33:00 -08:00
Wesley W. Terpstra
7a1937242a coreplex: provide correct bus-width for ITIM blockers 2017-11-18 14:32:37 -08:00
Henry Cook
9e0c26f855
Merge pull request #1118 from freechipsproject/basic-bus-blocker-3 
tile: bus blocker needs to know width
 2017-11-17 21:57:20 -08:00