Andrew Waterman
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6f028b2d52
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Increase BTB size; fix Rocket FPU bug
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2014-01-17 03:53:08 -08:00 |
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Andrew Waterman
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a43cf9d688
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Update to new privileged ISA
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2013-11-25 04:45:06 -08:00 |
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Yunsup Lee
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1d6d4b4e96
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move htif to uncore
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2013-11-07 13:19:19 -08:00 |
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Stephen Twigg
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36dfff5ee8
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Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy.
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2013-09-25 01:21:41 -07:00 |
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Andrew Waterman
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b7d7ced41b
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Update to new ISA
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2013-09-21 06:40:23 -07:00 |
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Huy Vo
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09247c0e0b
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fix to sram init pins
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2013-09-19 20:12:10 -07:00 |
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Andrew Waterman
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80003b3019
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Support RoCC
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2013-09-15 04:25:26 -07:00 |
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Andrew Waterman
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fbdbb01232
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update to new isa; disable vector tests
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2013-09-12 17:04:03 -07:00 |
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Henry Cook
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b42e140e05
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NetworkIOs no longer use thunks
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2013-09-10 16:23:52 -07:00 |
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Stephen Twigg
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6cde69e95d
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Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
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2013-09-09 14:31:18 -07:00 |
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Yunsup Lee
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ba9bbc27df
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apply same change to fpga top-level
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2013-08-24 15:50:03 -07:00 |
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Yunsup Lee
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76cd90fc01
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parameterize number of SCRs
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2013-08-24 15:47:42 -07:00 |
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Yunsup Lee
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0884bc9789
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fix DRAMSideLLCNull entries
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2013-08-24 13:20:38 -07:00 |
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Yunsup Lee
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1e3ac0afa9
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back to NTILES=1
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2013-08-24 13:10:30 -07:00 |
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Henry Cook
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b06d33da2f
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Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
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2013-08-19 19:54:41 -07:00 |
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Henry Cook
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85e5ce046f
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pulled submodule commits, uncore sbt standardized
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2013-08-15 17:07:13 -07:00 |
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Henry Cook
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6b20556661
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Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts:
chisel
riscv-hwacha
riscv-rocket
uncore
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2013-08-15 16:39:30 -07:00 |
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Henry Cook
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784e017bae
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Final Reg standardization
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2013-08-15 16:37:58 -07:00 |
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Henry Cook
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9b70ecf546
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Reg standardization
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2013-08-13 17:53:19 -07:00 |
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Huy Vo
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cc6631ae4d
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reset -> _reset
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2013-08-12 20:52:55 -07:00 |
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Henry Cook
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11e131af47
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initial attempt at upgrade
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2013-08-12 10:46:22 -07:00 |
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Henry Cook
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199e76fc77
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:31:27 -07:00 |
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Henry Cook
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4d916b56e3
|
Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.
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2013-07-24 23:28:43 -07:00 |
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Henry Cook
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2796de01bf
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new tilelink arbiter types, reduced release xact trackers
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2013-07-09 15:41:27 -07:00 |
|
Henry Cook
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896179cbb6
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removed bad mt test
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2013-06-14 00:14:18 -07:00 |
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Henry Cook
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c06cbf523b
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Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.
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2013-05-23 15:26:20 -07:00 |
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Henry Cook
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6a69d7d7b5
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pass closure to generate bank addr
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2013-05-23 14:58:19 -07:00 |
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Andrew Waterman
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d825c9d6e9
|
make fpga Makefile work with updated Makefrag
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2013-05-02 05:09:45 -07:00 |
|
Andrew Waterman
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cfa86dba4f
|
add FPGA test bench
The memory models now support back pressure on the response.
|
2013-05-02 04:59:32 -07:00 |
|
Andrew Waterman
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50bd9a08a7
|
resynchronize fpga uncore
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2013-05-01 01:12:47 -07:00 |
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Yunsup Lee
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93df795e48
|
change LLC leaf SRAM size
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2013-04-22 11:06:50 -07:00 |
|
Huy Vo
|
2ac3fd5306
|
get rid of init_node
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2013-04-20 01:36:32 -07:00 |
|
Huy Vo
|
0d87e3bacc
|
fixed init pin generation
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2013-04-20 00:38:01 -07:00 |
|
Henry Cook
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a01cdf95fd
|
tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps
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2013-04-10 13:53:27 -07:00 |
|
Henry Cook
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16ad8a7e9c
|
Fixes after merge
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2013-03-25 19:14:38 -07:00 |
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Andrew Waterman
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8e926f8d79
|
remove aborts
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2013-03-25 17:01:46 -07:00 |
|
Henry Cook
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eec590c1bf
|
Added support for multiple L2 banks. Moved tile IO queueing.
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2013-03-25 17:01:46 -07:00 |
|
Henry Cook
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806f897fc4
|
nTiles -> nClients in LogicalNetworkConfig
|
2013-03-25 17:01:46 -07:00 |
|
Andrew Waterman
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ce4c1aa566
|
remove aborts
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2013-03-25 17:01:46 -07:00 |
|
Henry Cook
|
cf76665d09
|
writebacks on release network pass asm tests and bmarks
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2013-03-25 17:01:46 -07:00 |
|
Henry Cook
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a0dc8d52d6
|
using new network and l2 controller
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2013-03-25 17:01:46 -07:00 |
|
Yunsup Lee
|
9efe71412f
|
add DRAMSideLLCNull
|
2013-03-19 00:43:34 -07:00 |
|
Andrew Waterman
|
4077b22929
|
include fesvr as a library; improve harnesses
|
2013-01-24 23:57:23 -08:00 |
|
Yunsup Lee
|
516a64f576
|
commit vec=true
|
2013-01-22 20:24:33 -08:00 |
|
Henry Cook
|
bb5c465bb3
|
Switched back to old, better-tested hub on master
|
2013-01-22 19:57:31 -08:00 |
|
Henry Cook
|
5b82d72eb7
|
New TileLink bundle names
|
2013-01-21 17:19:07 -08:00 |
|
Henry Cook
|
72bba81a76
|
now using single-ported coherence master
|
2013-01-16 23:58:24 -08:00 |
|
Henry Cook
|
e33648532b
|
Refactored packet headers/payloads
|
2013-01-15 15:57:06 -08:00 |
|
Henry Cook
|
a922b60152
|
Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor
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2013-01-07 14:23:49 -08:00 |
|
Henry Cook
|
f2cef8d8d2
|
new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
|
2013-01-07 14:19:55 -08:00 |
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