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riscv
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rocket-chip
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f2cef8d8d2
rocket-chip
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src
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main
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scala
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Henry Cook
f2cef8d8d2
new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
2013-01-07 14:19:55 -08:00
..
.gitignore
reference chip design
2012-10-09 13:05:56 -07:00
RocketChip.scala
new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
2013-01-07 14:19:55 -08:00