riscv/rocket-chip
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452 Commits

Author SHA1 Message Date
Howard Mao
e5cccc0526 don't update xact_vol_irel if not a voluntary irel 2016-07-18 17:05:23 -07:00
Howard Mao
84098db81f add a TileLinkTestRAM 2016-07-15 11:03:26 -07:00
Howard Mao
b122a54c32 don't allow more outer IDs than inner IDs 2016-07-13 12:42:28 -07:00
Howard Mao
de1e25f3d1 reduce usage of CAMs in converters 2016-07-13 11:20:50 -07:00
Howard Mao
8aa73915a1 put locking arbiter back into converter 2016-07-08 09:31:33 -07:00
Howard Mao
a50ba39ea7 Revert "add buffering and locking to TL -> Nasti converter" 
This reverts commit 2109a48e18719383942d535ff4c1d0a859dcc424.

Conflicts:
	src/main/scala/converters/Nasti.scala
 2016-07-08 09:31:33 -07:00
Andrew Waterman
70b677ecda Vec considered harmful; use isOneOf instead (#64) 
Vec is heavyweight and really should only be used for I/O and
dynamic indexing.  A recurring pattern in uncore is

    Vec(const1, const2, const3) contains x

which is nice but has a deleterious effect on simulation copilation
and execution time.  This patch proposes an alternative:

    x isOneOf (const1, const2, const3)
    x isOneOf seqOfThings

I think it's also more idiomatic.

This is just a prototype; I'm not wed to the name or implementation.
 2016-07-07 19:25:57 -07:00
Howard Mao
16a6b11081 fix bug in AXI -> TL converter 2016-07-07 14:34:24 -07:00
Howard Mao
7cc64011fb simplify amo_mask generation 2016-07-07 12:14:45 -07:00
Howard Mao
1c5e7be75b make sure Nasti write channel id is set correctly 2016-07-07 12:14:02 -07:00
Howard Mao
8ccc50a8f0 fix IdMapper and TL -> NASTI converter 2016-07-07 10:16:44 -07:00
Howard Mao
5d8d5e598b add buffering and locking to TL -> Nasti converter 2016-07-06 16:51:45 -07:00
Howard Mao
b10d306b4a add option to log L2 cache transactions for easier debugging 2016-07-06 14:59:09 -07:00
Howard Mao
64afc795fd make sure voluntary releases don't get allocated to L2WritebackUnit 2016-07-06 14:10:45 -07:00
Howard Mao
b105076996 fix ID mapper to disallow two in-flight requests with the same inner ID 2016-07-05 17:41:46 -07:00
Howard Mao
af76837970 conform to new NastiWriteDataChannel interface 2016-07-05 17:41:46 -07:00
Albert Ou
4c07aedfad Rewrite BRAMSlave to infer a single BRAM instance 2016-07-05 14:21:21 -07:00
Howard Mao
702444709a make sure pending bits updated for all releases 2016-07-05 12:08:22 -07:00
Howard Mao
06ed9c5794 add a single-entry queue in front of acquire and release for bufferless broadcast hub 2016-07-05 12:08:22 -07:00
Howard Mao
67bac383e3 hopefully fixed last bugs in Bufferless 2016-07-05 12:08:22 -07:00
Howard Mao
a35388bc27 fix merging of same xact ID puts/gets 2016-07-05 12:08:22 -07:00
Howard Mao
51f7bf1511 fix Bufferless voluntary release issue 2016-07-05 12:08:22 -07:00
Howard Mao
afc51c4a35 make sure TL -> NASTI converter handles multibeat transactions properly 2016-07-05 12:08:22 -07:00
Andrew Waterman
85808f8cbb Clean up PseudoLRU code 2016-07-02 15:09:12 -07:00
Howard Mao
caa9ca24b9 NASTI -> TL converter also uses ID mapper 2016-07-01 18:11:29 -07:00
Wesley W. Terpstra
39bee5198d Nasti Puts: decode wmask to determine addr_byte() and op_size() 
This change is TL0 specific; TL2 knows the op_size, and can use
this to do a much simpler one-hot decode of the address.
 2016-07-01 16:49:32 -07:00
Howard Mao
e163a23583 fix another bug in Widener 2016-07-01 16:24:48 -07:00
Howard Mao
10a46a36ae fix full_addr() function in TileLink 2016-07-01 15:17:41 -07:00
Howard Mao
61e3e5b45a more WIP on fixing Bufferless 2016-06-30 18:29:51 -07:00
Howard Mao
0eedffa82f WIP: Fix BufferlessBroadcastHub 2016-06-30 18:29:51 -07:00
Howard Mao
ce46f523c9 make sure Widener uses proper parameters to generate acquire/grant 2016-06-30 18:17:16 -07:00
Howard Mao
a0b1772404 change TileLinkWidthAdapter interface 2016-06-30 15:50:23 -07:00
Howard Mao
9feca99d5d make PutBlock wmask argument match Put 2016-06-28 13:10:46 -07:00
Howard Mao
b936aa9826 refactor uncore files into separate packages 2016-06-28 13:10:46 -07:00
Andrew Waterman
97e74aec3a Merge RTC and PRCI 2016-06-27 23:06:07 -07:00
Howard Mao
ec5b9dfc86 make sure trackers can handle case where there are no caching clients 2016-06-27 16:29:51 -07:00
Howard Mao
a93a70c8ec make sure merged voluntary releases are handled properly 2016-06-27 11:40:32 -07:00
Andrew Waterman
354b81c8fe Remove legacy HTIF things 
The SCR file is gone, too, because it is tightly coupled.  The
general concept could be revived as a module that somehow connects
to (or is contained by) the debug module.
 2016-06-23 13:17:11 -07:00
Andrew Waterman
f57524e0c1 Remove FENCE.I from debug ROM; specialize for RV64 2016-06-23 00:01:26 -07:00
Howard Mao
e3391b36b2 get rid of MuxBundle now that MuxCase and MuxLookup are fixed 2016-06-21 10:43:44 -07:00
Howard Mao
719fffff40 make sure updates from irel and iacq gated by tracker allocation 2016-06-17 17:15:02 -07:00
Howard Mao
b75b6fdcda make sure no-data voluntary releases get tracked 2016-06-17 17:15:02 -07:00
Howard Mao
ebe95fa827 fix wmask buffer clearing in L2 agents 2016-06-16 15:34:31 -07:00
Howard Mao
aba13cee7f fix BRAM slave so that it can correctly take all TileLink requests 2016-06-16 15:34:31 -07:00
Howard Mao
e716661637 make sure merged no-alloc put still allocs if original put allocs 2016-06-16 15:34:31 -07:00
Howard Mao
7e43b1d889 fix mistaken dequeueing from roq in TileLink unwrapper 2016-06-16 15:34:31 -07:00
Howard Mao
2789e60b6b fix ignt_q logic 2016-06-16 15:18:58 -07:00
Henry Cook
16bfbda3c9 Refactor the TransactionTracker logic in all the L2 TileLink Managers. 
They now share common sub-transactions within traits, and use a common
set of state transitions and scoreboarding logic. Tracker allocation
logic has also been updated. No changes to external IOs or the TileLink protocol.
A new bufferless Broadcast hub is also included, but does not yet pass fuzzing checks.
 2016-06-16 15:18:48 -07:00
mwachs5
2d2096e509 Add smaller ROM/RAM for 32-bit debug (#60) 2016-06-15 15:07:43 -07:00
Palmer Dabbelt
e5cfc2dac1 Add a Smi to TileLink converter (#59) 
I'm trying to get someone to attach their stuff to Rocket Chip for the
upcoming tapout.  TileLink sounded too complicated, but Smi went over
well.  Since the mmioNetwork in Rocket Chip is based on TileLink, it
seemed like the easiest thing to do was to write a TileLink to Smi
converter so people could use it.

It turns out there was already one inside the groundtest unit tests, so
I just moved that into uncore (it was inlined into a test case so you
couldn't actually use it before).  Internally the converter uses Nasti,
but I figured that's good enough for now.
 2016-06-10 14:04:28 -07:00