| .. |
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ahb.scala
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ahb: allow no-ops to progress also when a slave is !hready
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2016-06-09 10:41:12 -07:00 |
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amoalu.scala
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ahb: amoalu does not need so many parameters! (i want to reuse it)
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2016-05-24 14:58:27 -07:00 |
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bram.scala
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fix BRAM slave so that it can correctly take all TileLink requests
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2016-06-16 15:34:31 -07:00 |
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broadcast.scala
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make sure updates from irel and iacq gated by tracker allocation
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2016-06-17 17:15:02 -07:00 |
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bufferless.scala
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make sure updates from irel and iacq gated by tracker allocation
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2016-06-17 17:15:02 -07:00 |
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builder.scala
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Add config classes to drive unit testing of L2 TileLink agents.
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2016-05-20 16:15:43 -07:00 |
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cache.scala
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make sure updates from irel and iacq gated by tracker allocation
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2016-06-17 17:15:02 -07:00 |
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coherence.scala
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get rid of MuxBundle now that MuxCase and MuxLookup are fixed
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2016-06-21 10:43:44 -07:00 |
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consts.scala
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Add M_FLUSH_ALL command
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2016-05-31 19:25:31 -07:00 |
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converters.scala
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get rid of MuxBundle now that MuxCase and MuxLookup are fixed
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2016-06-21 10:43:44 -07:00 |
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debug.scala
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Remove FENCE.I from debug ROM; specialize for RV64
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2016-06-23 00:01:26 -07:00 |
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directory.scala
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First pages commit
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2015-04-29 13:18:26 -07:00 |
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dma.scala
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get rid of MuxBundle now that MuxCase and MuxLookup are fixed
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2016-06-21 10:43:44 -07:00 |
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ecc.scala
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Avoid floating-point arithmetic where integers suffice
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2016-06-01 21:59:02 -07:00 |
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htif.scala
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Work around zero-width wire limitation in HTIF
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2016-05-25 20:39:53 -07:00 |
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interconnect.scala
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Cope with changes to AddrMap
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2016-06-03 13:48:09 -07:00 |
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metadata.scala
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Refactor the TransactionTracker logic in all the L2 TileLink Managers.
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2016-06-16 15:18:48 -07:00 |
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network.scala
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Use buses, rather than crossbars, by default in TLInterconnect
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2016-05-26 16:10:42 -07:00 |
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package.scala
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First pages commit
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2015-04-29 13:18:26 -07:00 |
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plic.scala
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Update PLIC addr map
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2016-06-05 23:04:51 -07:00 |
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prci.scala
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Avoid need for cloneType
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2016-06-05 23:47:56 -07:00 |
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rom.scala
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Fix arithmetic in ROM row count
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2016-06-01 21:59:02 -07:00 |
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rtc.scala
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rtc: fix acquire message type check
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2016-05-25 20:37:48 -07:00 |
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scr.scala
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print the base address of each SCR as indicated
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2016-04-28 16:31:56 +01:00 |
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sdq.scala
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make sure updates from irel and iacq gated by tracker allocation
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2016-06-17 17:15:02 -07:00 |
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smi.scala
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Add a Smi to TileLink converter (#59)
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2016-06-10 14:04:28 -07:00 |
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tilelink.scala
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Refactor the TransactionTracker logic in all the L2 TileLink Managers.
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2016-06-16 15:18:48 -07:00 |
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trackers.scala
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make sure updates from irel and iacq gated by tracker allocation
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2016-06-17 17:15:02 -07:00 |
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uncore.scala
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Refactor the TransactionTracker logic in all the L2 TileLink Managers.
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2016-06-16 15:18:48 -07:00 |
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util.scala
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get rid of MuxBundle now that MuxCase and MuxLookup are fixed
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2016-06-21 10:43:44 -07:00 |
