riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman e9d3a650a4 Speed up C++ compilation 2014-01-31 12:25:19 -08:00
Andrew Waterman 0ce98a7e0c Update riscv-tools 2014-01-28 03:52:55 -08:00
Andrew Waterman fb827abbfa Use dynamic fesvr library 2014-01-28 03:50:19 -08:00
Andrew Waterman 7c11cf49b8 Update riscv-tools 2014-01-21 16:23:32 -08:00
Andrew Waterman b6c6bddb62 Add full CSRRx support and an asm test 2014-01-21 16:20:24 -08:00
Andrew Waterman 6f7ae01b1a More FPU fixes 2014-01-17 14:10:10 -08:00
Andrew Waterman 6f028b2d52 Increase BTB size; fix Rocket FPU bug 2014-01-17 03:53:08 -08:00
Andrew Waterman dfc13236d1 Linux works again! 2014-01-16 12:44:29 -08:00
Andrew Waterman d99ee1f9c2 Update hardfloat, fixing SFMA unit 2013-12-09 20:31:58 -08:00
Andrew Waterman ab6cd9c9e8 Update chisel, rocket 2013-12-09 15:09:48 -08:00
Andrew Waterman a43cf9d688 Update to new privileged ISA 2013-11-25 04:45:06 -08:00
Andrew Waterman a875233be6 update subrepos 2013-10-29 21:17:07 -07:00
Andrew Waterman 3c1d1f7981 Fix(?) SBT race by defining subproject build order 2013-10-29 13:27:36 -07:00
Andrew Waterman 8c380a7c3a Abort "make run" when tests fail 2013-10-29 13:25:57 -07:00
Andrew Waterman c55eee7244 Pass target machine exit code back to host OS 2013-10-29 13:24:09 -07:00
Andrew WatermanandHenry Cook 8e926f8d79 remove aborts 2013-03-25 17:01:46 -07:00
Andrew WatermanandHenry Cook ce4c1aa566 remove aborts 2013-03-25 17:01:46 -07:00
Andrew Waterman bbd010750f add missing #include 2013-01-06 04:53:40 -08:00
Andrew Waterman fd727bf8aa add some of the zedboard fpga infrastructure 
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
 2013-01-06 03:58:10 -08:00
Andrew Waterman 03df2c3766 update .gitignores 2013-01-06 03:58:10 -08:00
Andrew Waterman 10a6a42a4a make vlsi use dram model by default 2012-12-06 03:13:45 -08:00
Andrew Waterman d911e635d6 simplify c++ memory models; support +dramsim flag 
works for both vlsi and emulator
 2012-12-04 07:04:26 -08:00
Andrew Waterman 5dfb388f03 update to newest rocket 2012-11-27 02:43:31 -08:00
Andrew Waterman ea7029484e update to latest rocket 2012-11-26 20:57:12 -08:00
Andrew Waterman e12af07722 update to newest rocket 2012-11-25 04:40:46 -08:00
Andrew Waterman 9372912a9c update to newest rocket 2012-11-20 05:42:44 -08:00
Andrew Waterman 6d47d18c2b catch sigterm to gracefully exit (fixes vcd) 2012-11-20 05:40:44 -08:00
Andrew Waterman 7330deb13a print stack trace if elaboration fails 2012-11-20 05:39:48 -08:00
Andrew Waterman 7bcf59a18f support continous compilation via "make test" 
for c++ emulator only, for now
 2012-11-17 19:58:18 -08:00
Andrew Waterman b58214d7e3 remove more global constants 2012-11-17 17:25:43 -08:00
Andrew Waterman cf05b604b3 upgrade to new rocket; improve vlsi makefiles 2012-11-17 07:21:29 -08:00
Andrew Waterman 672e904c86 update to new rocket/uncore 2012-11-16 02:41:50 -08:00
Andrew Waterman e2afae011a factor out global constants 2012-11-06 08:18:40 -08:00
Andrew Waterman 0c372fc9ec refactor I$ config into RocketConfiguration 2012-11-04 17:00:19 -08:00
Andrew Waterman 4ed2d614a2 update to new rocket; retime fpu in dc-syn 2012-11-04 16:43:02 -08:00
Andrew Waterman 367b5489d1 first crack at continuous compilation/testing flow 
try it out: cd emulator; make test
 2012-10-19 04:09:07 -07:00
Andrew Waterman 1ad928cfe2 directly integrate dramsim build 
also, build it as a static library to simplify dependencies
 2012-10-18 18:59:37 -07:00
Andrew Waterman edf0eeed01 integrate updated rocket/uncore 2012-10-18 17:51:41 -07:00
Andrew Waterman 7fd4eb6afd update uncore 2012-10-09 18:05:32 -07:00
Andrew Waterman c3236e6ee6 add missing symlink and update uncore 2012-10-09 17:51:33 -07:00