Henry Cook
71ddd797bf
Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i
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Added coverage point to cover the case when ECC error happens during …
2017-12-01 18:00:11 -08:00
Gleb Gagarin
7c2df9f0bf
Cover the case when there is an ECC error in DCache data array during fence.i execution
2017-12-01 16:28:28 -08:00
Gleb Gagarin
74bd61c556
Added coverage point to cover the case when ECC error happens during fence.i execution
2017-12-01 15:50:31 -08:00
Wesley W. Terpstra
8781d2b2e7
diplomacy: provide a val name for all LazyModule constructions
2017-12-01 11:28:21 -08:00
Wesley W. Terpstra
fe8d557751
PeripheryBus: automatically disappear when not used
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
93c8010aca
FrontBus: automatically disappear when not used
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
e489c4226e
diplomacy: remove node arity and allow empty Nexus nodes (Xbars)
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This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.
val x = TLXbar()
x := master
slave := x
val y = TLXbar()
x :=* y // only connect y if it gets used
This will create crossbar x, but crossbar y will disappear.
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
6a25a3b7ac
tilelink: we can have helper objects for terminal nodes now too!
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The new rule is you should have an object.apply method if you only have a
single .node.
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
2092cb4ec8
diplomacy: reprotect Node bundles after module construction is completed
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
fdeed7bbb3
unittest: add an API for describing LazyModule unit tests
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
cc789e9063
diplomacy: protect more of the unstable API
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
8ed9e78903
diplomacy: support cloning of LazyModules
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
b43bcdfcd1
CloneModule: beat chisel into submission
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
1f23f9f865
diplomacy: categorize parameter resolution by direction+side
2017-12-01 11:26:59 -08:00
Wesley W. Terpstra
fbbfc9c096
diplomacy: include edge type in inward/outward node handles
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This is necessary capture the node implementation in the handle,
which is in turn necessary to support cloning a Node.
2017-12-01 11:26:58 -08:00
Wesley W. Terpstra
35506279af
regmapper: fix d_ready => d_bits loop in RegField.bytes
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RegField.bytes updates only those bytes which are written every cycle.
However, there was a bug that it would try to return the updated value on reads.
This led to another TL-spec violating combinational path, just like the Debug module.
2017-11-30 16:38:45 -08:00
Wesley W. Terpstra
fc1f5be316
Debug: fix a latent combinational loop (d_ready => d_bits)
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When passed a Wire, WNotify outputs that wire on reads wire => d_bits.
Furthermore, it updates the Wire when a write occures d_ready => wire.
These registers should be returning undefined value on read, anyway.
2017-11-30 16:36:45 -08:00
Richard Xia
a447343074
Merge pull request #1129 from freechipsproject/add-exception-cover-properties
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Add cover properties for exceptions in the core.
2017-11-30 16:23:14 -08:00
Richard Xia
4bd9c477ea
Add cover properties for ECALL exceptions.
2017-11-30 14:27:04 -08:00
Richard Xia
29c70501f2
Add cover properties for exceptions in the core.
2017-11-30 14:27:04 -08:00
Andrew Waterman
890528c641
Avoid data corruption under correctable tag error during flush
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This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable. Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 16:09:44 -08:00
Andrew Waterman
34d86ef665
Revert "Avoid data corruption under correctable tag error during flush ( #1130 )"
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This reverts commit 44eb4d12b5
.
2017-11-29 16:09:30 -08:00
Andrew Waterman
44eb4d12b5
Avoid data corruption under correctable tag error during flush ( #1130 )
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This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable. Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
2017-11-29 09:42:00 -08:00
Megan Wachs
f554ad7e2c
debug: Remove workaround for Chisel 3 #527
2017-11-27 10:50:15 -08:00
Andrew Waterman
5155eb6059
Don't emit writeback state machine logic for scratchpad ( #1127 )
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Firrtl can't DCE it because it would require analyzing the state machine.
2017-11-22 18:40:02 -06:00
Wesley W. Terpstra
6f3ff634f2
DTS: collect common DTS nodes and move timebase-frequency to cores
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Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.
timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
2017-11-20 18:09:57 -08:00
Wesley W. Terpstra
3b299397db
diplomacy: bind resources to outer-most binding
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This is probably the wrong thing to do, but it is expedient for now.
We need a better way to do cross-coreplex visibility.
2017-11-20 17:42:08 -08:00
Wesley W. Terpstra
44f99cd9a5
diplomacy: eliminate redundant bindings
2017-11-20 17:42:08 -08:00
Wesley W. Terpstra
baa31edf7d
RocketTile: if the dcache is incoherent, report it in DTS
2017-11-20 17:42:06 -08:00
Yunsup Lee
a60d7d419d
icache: add a couple cover points for I$ and ITIM iteraction
2017-11-20 13:14:38 -08:00
Andrew Waterman
5e94884f09
Fix ITIM deallocation during I$ refill causing data corruption
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Deallocation can change repl_way, which violates the assumption that it
remains constant throughout refill.
The workaround described in commit 3db066303b
still suffices, provided only the hart that owns the ITIM changes the ITIM
allocation.
This subsumes commit 3db066303b
.
2017-11-20 12:30:40 -08:00
Andrew Waterman
66b7a8a5ed
Revert "Fix ITIM bug overwriting I$ contents when deallocating ITIM ( #1079 )"
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This reverts commit 3db066303b
.
2017-11-20 12:26:04 -08:00
Wesley W. Terpstra
ec809483b0
BusBypass: assert fail if the widths of the two slaves do not match
2017-11-18 14:37:27 -08:00
Wesley W. Terpstra
c475c78c2f
BusBlocker: don't provide an (incorrect) default value for width
2017-11-18 14:33:00 -08:00
Wesley W. Terpstra
7a1937242a
coreplex: provide correct bus-width for ITIM blockers
2017-11-18 14:32:37 -08:00
Henry Cook
f3575404c0
tile: bus blocker needs to know width :(
2017-11-17 20:17:17 -08:00
Henry Cook
b625e68360
tile: put a BasicBusBlocker inside RocketTile ( #1115 )
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...instead of on the master side of the system bus.
People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
2017-11-17 17:26:48 -08:00
Megan Wachs
e7704f46c8
Add some add'l debug features ( #1112 )
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* debug: Update macros from spec
* debug: some corrections in the auto-generated files
* debug: update renamed fields
* Debug: implement the implicit ebreak option for small program buffers
* debug: clean up some unused code and add more require() explanations
* debug: make implicit ebreak false
* debug: Add the havereset/haveresetack functionality
* debug: program buffer can still be 16 even if there is an implicit ebreak
2017-11-16 17:14:41 -08:00
Wesley W. Terpstra
61ef560c75
tilelink: don't pollute TLParamters with AtomicAutomata's implementation ( #1111 )
2017-11-14 17:49:10 -08:00
Wesley W. Terpstra
8b79f0394e
Merge pull request #1105 from freechipsproject/axi4-xbar
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axi4: add an Xbar
2017-11-14 16:18:23 -08:00
Wesley W. Terpstra
509a48c9c9
TLToAXI4: block TL early source re-use before it goes to AXI4 ( #1110 )
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This is a follow-up to PR #1108 .
Rather than increasing the number of transactions we allow to be inflight,
instead just block TL when early source re-use happens. This is a better
fix since it means we don't pay mostly wasted downstream hardware to handle
an additional transaction inflight that almost never happens.
2017-11-14 16:08:43 -08:00
Wesley W. Terpstra
e370934c50
AXI4Xbar: reduce number of special cases
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
9004ecdf25
unittest: include AXI4Xbar in regression
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
5875017956
axi4: add an Xbar
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
72c89f7e30
axi4: add a Filter suitable for manipulating test visibility
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
bfc0ba679a
axi4: add a Delayer for unit tests
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
1902ba063a
Filter: can claim to be out-of-order when you are not
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
58a93e2100
AXI4SRAM: handy helper object
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
353ddffc11
RAMModel: add a convenience object
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
7cfb69e2d5
Queue: silence some warnings
2017-11-14 15:09:09 -08:00
Wesley W. Terpstra
147fad6387
Fix AXI4 FIFO ordering for masters with early source reuse ( #1108 )
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* TLToAXI4: fix WaR for single-source FIFO masters
* TLToAXI4: fix potential counter overflow => WaR hazard
If you have a FIFO master with 2^n-1 sources that performs early
source re-use, the old code could potentially break FIFO order.
2017-11-13 20:32:09 -08:00
Henry Cook
7098ebf439
rocket: fix itim GetPropertyByHartId ( #1109 )
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needs to use RocketTileParams.hartid instead of zipWithIndex
2017-11-13 19:25:20 -08:00
Wesley W. Terpstra
0cfa801bfc
coreplex: allow MMIO to be misaligned ( #1103 )
2017-11-10 15:12:28 -08:00
Wesley W. Terpstra
a061b16ee3
coreplex: fix typo ( #1104 )
2017-11-10 15:11:56 -08:00
Andrew Waterman
4ebca73d59
Provide option to support AMOs only on I/O, not DTIM/D$
2017-11-09 17:45:53 -08:00
Andrew Waterman
efdb418559
Merge pull request #1098 from freechipsproject/frontend
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Frontend improvements
2017-11-09 17:44:38 -08:00
Andrew Waterman
d0c6cbba6b
Improve frontend branch prediction
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- Put correctness responsibility on Frontend, not IBuf, for improved
separation of concerns. Frontend must detect case that the BTB
predicts a taken branch in the middle of an instruction.
- Pass BTB information down pipeline unconditionally, fixing case that
screws up the branch history when the BTB misses and the instruction
is misaligned.
- Remove jumpInFrontend option; it's now unconditional.
- Default to one-bit counters in the BHT. For tiny BHTs like these, it's
more resource efficient to have a larger index space than to have
hysteresis.
2017-11-09 00:00:56 -08:00
Andrew Waterman
bb9d8264e2
"Correct" ITIM uncorrectable errors
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This permits forward progress when a core wants to handle its own
uncorrectable ITIM errors. Previously, another core had to do it.
2017-11-08 22:15:03 -08:00
Andrew Waterman
5c1b34d854
Don't report a TL error if overwriting a whole ITIM word
2017-11-08 22:15:03 -08:00
Andrew Waterman
9b16d25861
Fix reporting of ITIM error addresses on slave-port accesses
2017-11-08 22:15:03 -08:00
Wesley W. Terpstra
b59880fe8e
Fragmenter: add an option for earlyAck only on PutFulls ( #1095 )
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Fragmenter: add a third case for earlyAck (PutFulls only)
It seems quite common to have a device that is backed by ECC. When
performing a multibeat PutPartial, these devices can exhibit their
first error on the last beat (if it had an incomplete write mask
for that beat, which required read-write-modifying corrupted data).
Generally, these devices have ECC granularity <= the bus width. In
those cases, if you send a PutFull, the first beat carries the
error value for the whole burst. Consider:
If the PutFull was below the granularity, it was a single beat.
If the PutFull was multi-beat, it exceeds the granularity.
Therefore, an important variation on the earlyAck optimization is
the case where only PutFulls receive an earlyAck.
2017-11-08 15:31:19 -08:00
Andrew Waterman
4514adb77c
Merge pull request #1093 from freechipsproject/local-error-interrupt
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generate local interrupts on bus/ecc errors
2017-11-07 14:19:53 -08:00
Henry Cook
d096fd206b
coreplex: WithStatelessBridge => WithIncoherentTiles ( #1092 )
2017-11-07 13:47:56 -08:00
Andrew Waterman
34f38b0fb1
Don't permit vectoring of high interrupts
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Send them to the base of the vector to obviate an adder
2017-11-07 01:59:30 -08:00
Andrew Waterman
6176b348dc
Invalidate TL error bit in D$ once progress is made
2017-11-07 00:52:18 -08:00
Andrew Waterman
d8d4504995
Provide separate masks for local & global BusErrorUnit interrupts
2017-11-06 18:03:59 -08:00
Andrew Waterman
be3a3e0187
Generate local interrupt #128 on bus errors
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It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.
2017-11-06 18:03:59 -08:00
Andrew Waterman
ac096a89e7
Make BusErrorUnit support 32-bit stores
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Otherwise it isn't too useful for RV32!
2017-11-06 18:03:59 -08:00
Andrew Waterman
6357db0b12
Expose BusErrorUnit non-diplomatically for use as local interrupt
2017-11-06 18:03:59 -08:00
Andrew Waterman
bdda2cb145
Merge pull request #1089 from freechipsproject/aswaterman-patch-1
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Don't emit PTW covers when !usingVM
2017-11-06 18:03:36 -08:00
Andrew Waterman
95d00b13cc
Report ITIM slave port errors to BusErrorUnit
2017-11-06 12:39:17 -08:00
Andrew Waterman
c84848afa6
Report ITIM uncorrectable errors over D-channel
2017-11-06 12:32:45 -08:00
Wesley W. Terpstra
7cc7cd5992
tilelink: AtomicAutomata; add errors to the unit test
2017-11-06 12:05:44 -08:00
Wesley W. Terpstra
88234ead0d
tilelink: generalize ErrorEvaluator to more than just address patterns
2017-11-06 11:53:09 -08:00
Wesley W. Terpstra
25ea7fa852
tilelink: AtomicAutomata should OR the Get error with the Put error
2017-11-06 11:31:23 -08:00
Wesley W. Terpstra
dcf67b49fa
BusBypass: only stall A once the last beat is accepted ( #1090 )
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When switching ports, the bypass stalls new messages until all
outstanding messages have received their responses. However, this
stall must NOT stop the remaining beats of a partially sent request.
2017-11-06 11:13:15 -08:00
Andrew Waterman
989eeb78f9
Prevent some unnecessary pipeline replays
2017-11-06 11:04:06 -08:00
Andrew Waterman
c8bc487ab8
Use pseudo-LRU policy in BTB
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FIFO falls on its face if the working set doesn't fit in the BTB.
2017-11-03 16:27:04 -07:00
Andrew Waterman
f859da85ff
Disable covers that don't apply to DTIM
2017-11-03 15:38:13 -07:00
Andrew Waterman
d6ede818ee
DTIM doesn't accept grants
2017-11-03 15:37:48 -07:00
Andrew Waterman
7bef935d2a
Don't emit PTW covers when !usingVM
2017-11-03 15:03:27 -07:00
Wesley W. Terpstra
16116991e7
Fix stateless caching ( #1084 )
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* tilelink: ToAXI4 should format it's error message
* WithStatelessBridge: mark the memory bus incoherent and cacheable
... and hope that the user doesn't put more than one master down.
2017-11-01 11:05:56 -07:00
Wesley W. Terpstra
4ccdbecb63
Async covers ( #1085 )
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* cover: support covering cross-product of ready-valid
* tilelink: AsyncCrossing now has covers for all flow control logic
2017-11-01 11:03:45 -07:00
Andrew Waterman
a2b80100e2
Make PseudoLRU policy support non-power-of-2 sizes
2017-11-01 01:47:23 -07:00
Wesley W. Terpstra
84145959e1
tilelink: fix error fragmentation from multibeat to multibeat ( #1082 )
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Unfortunately, dLast is not actually correct for AccessAckData.
dFragnum is 0 for all the subbeats in the multibeat=>multibeat case.
2017-10-31 17:34:46 -07:00
Wesley W. Terpstra
8ec06151b0
interrupts: Crossing should use asynchronously reset registers ( #1080 )
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Otherwise you can get interrupts wedged high from a domain that has
not yet been clocked/powered up.
2017-10-31 16:29:06 -07:00
Megan Wachs
f86489b59e
JTAG: Use sorted map for stability ( #1073 )
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* JTAG: Use sorted map for stability
Otherwise the generated FIRRTL/Verilog is non deterministic
* jtag : parens for clarity
* jtag: Use deterministic ListMap and sort for stability
* JTAG: use slightly clearer SortedMap (clearer to me anyway)
* jtag: whitespace cleanup
2017-10-31 15:33:41 -07:00
Andrew Waterman
3db066303b
Fix ITIM bug overwriting I$ contents when deallocating ITIM ( #1079 )
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Workaround: disable interrupts and then do:
.align 3
sb x0, (t0) # t0 contains ITIM-deallocate address
fence.i
2017-10-31 00:49:56 -07:00
Wesley W. Terpstra
45a904b396
ahb: ignore hrdata on an AHB error
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From the AHB spec:
"A slave only has to provide valid data when a transfer completes with an OKAY
response. ERROR responses do not require valid read data."
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
6318d7d44c
ahb: inject fuzzy errors
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
2912a76a2b
axi4: inject fuzzy errors
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
e8ed450f13
unit tests: do not use LFSR16 which has a common seed!
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We want each LFSR to generate independent noise.
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
ec70e5fb02
apb: inject fuzzy errors
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
0280a1f218
tilelink: add the ErrorEvaluator, a test bench error helper
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
2d12ddb4ed
tilelink: ToAXI4 makes R channel errors sticky
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
d6f1612812
tilelink: ToAHB should make read errors sticky as well
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
4c9d9c6331
tilelink: optimize WidthWidget error circuit to nothing
2017-10-30 21:09:45 -07:00
Wesley W. Terpstra
0992a459be
tilelink: Fragmenter should combine errors
2017-10-30 21:09:42 -07:00
Wesley W. Terpstra
13d0bf6808
tilelink: Monitor now enforces spec-defined error rules
2017-10-30 11:27:07 -07:00
Wesley W. Terpstra
a954f020a9
diplomacy: use new node style chaining
2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
6aac658184
diplomacy: convert all helper objects to return nodes
2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
41705808dd
Bus: remove deprecated crossing attach methods
2017-10-28 11:34:16 -07:00
Wesley W. Terpstra
7cf5d4aa90
diplomacy: define only primary node types
2017-10-28 11:16:56 -07:00
Wesley W. Terpstra
eeb11a2693
coreplex: eliminate dead code
2017-10-27 01:13:35 -07:00
Wesley W. Terpstra
9f83db998e
tile: don't chain too many unneeded TileLink adapters ( #1075 )
2017-10-27 01:12:58 -07:00
Wesley W. Terpstra
e12bdfdf9b
coreplex: attach example external interrupts ( #1076 )
...
Fixes #1071
2017-10-27 01:12:42 -07:00
Wesley W. Terpstra
13981379c4
CoreplexClockCrossing: add a helper method to decide if a clock is useul ( #1074 )
2017-10-26 23:39:56 -07:00
Wesley W. Terpstra
1d8e539362
coreplex: confirm crossings actually cross the right boundary
2017-10-26 15:53:01 -07:00
Wesley W. Terpstra
60284082e7
diplomacy: add a hook for injecting code into LazyModule.module scope
2017-10-26 15:19:05 -07:00
Wesley W. Terpstra
a060c37173
diplomacy: expose the API to query a Node for its neighbours
2017-10-26 15:08:06 -07:00
Wesley W. Terpstra
e2d6d4d725
diplomacy: eliminate bindings dead-code
2017-10-26 15:02:21 -07:00
Wesley W. Terpstra
9e33ccdb05
rocket: clarify intent of boundaryBuffers and move to RocketTile
2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
e76e0f6dce
interrupts: add debugstring to nodes to show sync depth in graphml
2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
2acff8d21f
util: delete old long-deprecated crossing code
2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
da7703aee9
crossings: deprecate non-island crossing style
2017-10-26 13:58:52 -07:00
Wesley W. Terpstra
76df1397e0
crossings: stop using deprecated APIs in tests
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
380cc6f03b
axi4: now also supports the island pattern
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
05d48d1807
TLBuffer: replace TLBufferChain with TLBuffer.chain
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
ce2b904b19
coreplex: tidy up interrupt crossings
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
e30906589f
coreplex: refactor crossings to use node pattern
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
6276ea4291
diplomacy: it possible for NodeHandles to put indirection on their attachment
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
8c5e8dd071
coreplex: leverage improved := composition
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
e894d64bca
diplomacy: support := composition
...
This makes it possible to treat chained composition associatively.
x := y :=? z :=* a ...
It also makes it easy to chain multiple optional adapters:
node :=? (Seq(a, b) ++ c ++ d)
2017-10-26 13:04:32 -07:00
Henry Cook
b48ab985d0
coreplex: RocketTileWrapper now HasCrossingHelper
2017-10-26 13:04:32 -07:00
Henry Cook
9fe35382ea
sbus: tile adapters in sbus scope
2017-10-26 13:04:32 -07:00
Henry Cook
95a2e6ef27
coreplex: improve tile attachment adapters
2017-10-26 13:04:32 -07:00
Wesley W. Terpstra
2175758050
interrupts: implement in crossing wrapper
2017-10-26 13:04:29 -07:00
Wesley W. Terpstra
c6f95570df
IntNodes: moved from tilelink to their own package
2017-10-25 16:56:51 -07:00
Wesley W. Terpstra
6bc9c9fc6c
coreplex: add a crossing wrapper to generalize the island pattern
2017-10-25 16:56:50 -07:00
Wesley W. Terpstra
7453186b59
diplomacy: add reflection for parent modules to nodes
2017-10-25 16:56:50 -07:00
Christopher Celio
c4978712c9
csr: allow for superscalar decode ( #1069 )
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* CSR provides a decode port to check for an illegal instruction.
* This commit now allows for multiple instructions in decode to get this
illegal instruction information.
* This commit leverages the existing decodeWidth parameter. This will
potentially over-provision the number of decode ports needed for
RVC-enabled cores.
Closes #1068
2017-10-25 13:58:26 -07:00
Wesley W. Terpstra
82b1aa8116
coreplex: print the A first to look nicer
2017-10-18 16:52:35 -07:00
Wesley W. Terpstra
a1ac23d7ec
coreplex: continue to print the device name in the address map
2017-10-18 16:44:53 -07:00
Richard Xia
5a951799aa
Add atomics support to DTS JSON file.
2017-10-18 15:17:53 -07:00
Megan Wachs
e9e05b5f3b
Add a check that MaxHartIdBits is enough for all hartids ( #1054 )
...
* Add a check that MaxHartIdBits is enough for all hartids
* Correct off-by-one error in hartid check
2017-10-13 15:20:35 -07:00
Henry Cook
1852ccd8f3
Merge pull request #1053 from freechipsproject/resource-cacheable
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tilelink: cacheable resource permission
2017-10-12 17:49:49 -07:00
Wesley W. Terpstra
8b58327fa4
axi4: conversion from TL does not need beatBytes ( #1051 )
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We used to pack the addr_lo into user bits. We don't do that anymore.
There is thus no need to waste those bits, nor to pass that arg.
2017-10-12 16:41:54 -07:00
Andrew Waterman
21b5367259
Expand C.UNIMP correctly ( #1052 )
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It was expanding to AMOADD.W, which is clearly not an illegal instruction.
2017-10-12 14:00:14 -07:00
Henry Cook
ad243ef9f5
tilelink: cacheable resource permission now reports whether a address space could possibly be cached, even if no visible adapters make it so
2017-10-12 13:49:40 -07:00
Henry Cook
ad543e5bb6
Merge pull request #1050 from freechipsproject/uncacheable-tims
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rocket: TIMs should never be cached
2017-10-12 13:04:00 -07:00
Wesley W. Terpstra
f82e441426
axi4: implement a diplomatic AXI4 clock crossing ( #1049 )
2017-10-12 00:05:45 -07:00
Henry Cook
66e4bfc2d9
rocket: TIMs should never be cached
2017-10-11 18:22:52 -07:00
Henry Cook
b64609bfe8
Merge pull request #1039 from freechipsproject/tile-crossing-params
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Improvements wrt connecting RocketTiles to SystemBus
2017-10-11 17:12:03 -07:00
Megan Wachs
7b4c48d005
Correctly hook up the Local Interrupts into the Coreplex. Name some IntXBars
2017-10-11 15:10:50 -07:00
Henry Cook
60934ac622
coreplex: TilePortParams use BasicBusBlockers
2017-10-11 13:36:46 -07:00
Henry Cook
2dbe882e58
tilelink: add BasicBusBlocker device
2017-10-11 13:36:42 -07:00
Henry Cook
9f8e3d8879
tilelink: BusBypass can be sent to DeadlockDevice
2017-10-11 12:45:36 -07:00
Henry Cook
ec056535dc
tilelink: add DeadlockDevice
2017-10-11 12:44:23 -07:00
Wesley W. Terpstra
b566ffedea
system: fix DefaultFPGAConfig ( #1047 )
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It was missing cores. Fixes #736 .
2017-10-11 10:48:41 -07:00
Henry Cook
329a5c35d4
tilelink: unsafe cache cork discards outer d.sink
2017-10-11 00:30:51 -07:00
Henry Cook
1240cb275c
coreplex: TilePortParams formatting
2017-10-11 00:29:11 -07:00
Wesley W. Terpstra
5d62c321f4
generator: create annotation file
2017-10-10 23:23:06 -07:00
Henry Cook
75345b6048
rocket: don't remove ports on top module
2017-10-10 21:28:59 -07:00
Wesley W. Terpstra
b3bdf5eca6
RegField: default argument for .bytes
2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
e094b94ce5
clint: use RegField.toBytes to save some work
2017-10-10 19:49:35 -07:00
Wesley W. Terpstra
10472b4296
diplomacy: auto connect bundles in a stable order ( #1045 )
2017-10-10 19:41:46 -07:00
Henry Cook
1867a5b226
rocket: only cache when AcquireT is possible
2017-10-10 18:06:58 -07:00
Andrew Waterman
b2bc46471b
Conditionalize some covers that are sometimes impossible ( #1043 )
2017-10-10 17:14:33 -07:00
Henry Cook
37406706b4
coreplex: move CacheCork in front of SBus
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Continue to not allow caches to cache ROMs.
Update TinyConfig and WithStatelessBridge.
2017-10-10 16:24:32 -07:00
Henry Cook
8f5f80f958
coreplex: TileSlavePortParams inject adapters into PBus
2017-10-10 15:25:08 -07:00
Henry Cook
660355004e
coreplex: TileMasterPortParams inject adapters into SBus
2017-10-10 15:02:50 -07:00
Andrew Waterman
50429daef4
Merge pull request #1036 from freechipsproject/l1-cover
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Add some covers for L1 memory system
2017-10-10 12:28:48 -07:00
Henry Cook
9026646459
coreplex: first cut at using RocketCrossingParams
2017-10-10 12:02:04 -07:00
Wesley W. Terpstra
d6766a8c68
RocketTile: make sure 'hartid' is available for traits ( #1037 )
2017-10-09 21:03:18 -07:00
Andrew Waterman
1474ab438d
Remove extraneous signal
2017-10-09 18:33:50 -07:00
Andrew Waterman
f3825270c1
Add some covers for L1 memory system
2017-10-09 18:33:36 -07:00
Andrew Waterman
2c4009a138
Fix paddrBits < xLen && paddrBits == vaddrBits case
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Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
2017-10-09 16:48:04 -07:00
Megan Wachs
0e6aa7ae9d
Merge pull request #1024 from freechipsproject/jtag_coverage
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Add Coverage points for JTAG TAP
2017-10-09 12:29:18 -07:00
Megan Wachs
0916cf1bdd
JTAG Coverage: Correct jtag_reset case
2017-10-09 09:54:15 -07:00
Megan Wachs
9efe1c448e
Merge remote-tracking branch 'origin/master' into HEAD
2017-10-09 09:48:38 -07:00
Andrew Waterman
986cbfb6b1
For Rockets without VM, widen vaddrBits to paddrBits
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This supports addressing a >39-bit physical address space.
2017-10-08 01:21:47 -07:00
Andrew Waterman
a0e5a20b60
Don't route branch comparison result through ALU output mux
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This potentially mitigates a critical path, and makes the ALU usable
in processors that have dedicated branch comparators.
2017-10-07 17:36:24 -07:00
Andrew Waterman
36c39d01e4
Factor out most of HasRocketTiles into HasTiles
2017-10-07 17:36:24 -07:00
Andrew Waterman
70a4127cb8
Factor out some of HaveRocketTiles into HaveTiles
2017-10-07 17:36:24 -07:00
Andrew Waterman
34e96c03b1
Move HCF to BaseTile
2017-10-07 17:36:24 -07:00
Andrew Waterman
71205b70cc
Make RocketTileWrapper a BaseTile
2017-10-07 17:36:24 -07:00
Andrew Waterman
4645b61fd3
Decouple BaseTile from HasTileLinkMasterPort
2017-10-07 17:36:24 -07:00
Henry Styles
5498468743
FPU : simplify pipeline register generation in FMA
2017-10-05 15:18:19 -07:00
Henry Styles
7a46715cbc
FPU : to assist retiming move upto first 2 register stages of into FMA
2017-10-05 15:18:04 -07:00
Wesley W. Terpstra
bd045a3b95
tilelink: split Acquire into Acquire{Block,Perm} ( #1030 )
...
We had planned for a while to add an 'Overwrite' message which obtains
permissions without requiring retrieval of data. This is useful whenever
a master knows it will completely replace the contents of a cache block.
Instead of calling it Overwrite, we decided to split the Acquire type.
If you AcquirePerm, you MUST Release and ProbeAck with Data.
2017-10-05 12:49:49 -07:00
Wei Song (宋威)
81b9ac42a3
add comments to diplomacy resource. ( #913 )
2017-10-05 12:45:56 -07:00
Henry Cook
8da7aabd51
tile: supply hartid from RocketTileParams
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make WithNCores partial configs override rather than append more tiles
2017-10-05 00:31:53 -07:00
Henry Cook
45581e60f0
Revert "Merge pull request #1027 from freechipsproject/dont-touch-hartid"
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This reverts commit 5232a29d7d
, reversing
changes made to a2dc13669a
.
2017-10-05 00:26:44 -07:00
Andrew Waterman
5a84564203
Merge pull request #1023 from freechipsproject/csr-cleanup
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Generalize CSR file to support simpler cores
2017-10-04 14:04:59 -07:00
Andrew Waterman
32fda51a2c
Get rid of paddrBits from SystemBus ( #1029 )
2017-10-04 12:11:37 -07:00
Andrew Waterman
7bcf28c585
Define fetchBytes in HasCoreParams, not Frontend
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It is more generally useful.
2017-10-03 17:34:18 -07:00
Andrew Waterman
2786e42d99
Don't register interrupts in CSRFile
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They are usually registered outside the tile in a CDC.
2017-10-03 17:34:18 -07:00
Andrew Waterman
5cfe070932
Add option to make misa read-only
2017-10-03 17:34:18 -07:00
Andrew Waterman
09468a272b
Add option to remove basic counters (mcycle/minstret)
2017-10-03 17:34:18 -07:00
Andrew Waterman
ab0821f25b
Move microarchitecture-neutral params from Rocket to Core
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This makes some of the units more reusable.
2017-10-03 17:34:18 -07:00
Andrew Waterman
190d5c50d9
Remove deprecated custom-CSR support
2017-10-03 17:34:18 -07:00
Henry Cook
5232a29d7d
Merge pull request #1027 from freechipsproject/dont-touch-hartid
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Make use of the new DontTouch annotation
2017-10-03 12:55:34 -07:00
Henry Cook
d33737802a
util: add DontTouch trait with dontTouchPorts method
2017-10-02 19:36:34 -07:00
Henry Cook
aa3a18222c
HellaCache: users like to peep resp.data and resp.addr
2017-10-02 19:36:30 -07:00
Henry Cook
cedfb0e784
coreplex: dontTouch the rocket_tile_inputs wire
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which contains hartid.
2017-10-02 19:36:10 -07:00
Wesley W. Terpstra
a2dc13669a
Error grants ( #1025 )
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* CacheCork: an error Grant still says 'toT' even though it is transient
Grants with errors must be handled by a client as though no actual
permissions were obtained, so that two clients do not both end up believing
that they own a block which is only temporarily offline. However, the
Grant MESSAGE should still match the request; ie. if you did Acquire.NtoT,
the response must be Grant.toT, even though the 'error' bit signals that
the Grant actually grants no permissions.
This keeps the implementation of request-response tracking in interstitial
adapters and FSMs simple, consistent with the way multibeat errors must
include all their beats.
* Error: handle permissions properly
2017-10-02 14:49:25 -07:00
Megan Wachs
9c9cb68462
JTAG Coverage: Add reset coverage points
2017-10-02 11:08:13 -07:00
Megan Wachs
a8ab06d572
JTAG: Add coverage points to the JTAG Tap
2017-10-02 11:08:13 -07:00
Jack Koenig
8891bf1b64
Bump chisel3 and firrtl, update plugin versions
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And update chisel3 code
2017-09-29 15:44:27 -07:00
Henry Cook
547bdc2b5b
diplomacy: standardize sram device resource naming ( #1022 )
2017-09-29 14:52:26 -07:00