97640f099d
Merge pull request #41 from ucb-bar/regressions
...
Support torture regressions
2016-02-01 18:39:28 -08:00
5cea4edee2
Bump riscv-tools for torture NaN ISA change
2016-01-31 23:06:59 -08:00
e18759642f
Avoid running Chisel in parallel in the same directory
...
It looks like Chisel fails when I try to run it in parallel. This adds a lock
file to ensure that only a single Chisel instance is running at a time when
running the regressions.
2016-01-31 23:06:59 -08:00
00465b15c3
Allow the regression Makefile to clean all targets
2016-01-31 23:06:59 -08:00
c9a2b7d109
Add torture as part of the regression
...
Since the latest Spike fix my torture runs are succeeding, so I can now run it
as part of the regression flow.
2016-01-31 23:06:59 -08:00
e185fe6850
Add targets for emulator and fsim regressions
...
This change allows the other simulation targets (the emulator and the FPGA
simulator) to be run just like the Verilog simulator could be before.
2016-01-31 23:06:59 -08:00
7e9d8c7256
Merge pull request #40 from ucb-bar/make-3.82
...
Support make-3.82 and newer
2016-01-28 14:28:27 -08:00
1149a412cc
Support make-3.82 and newer
...
make changed its priorties for resolving implicit rules, which causes different
behavior when running "make run-bmark-tests". This patch changes the hex file
rules to ensure they match between the two versions of make.
I've tried this with both make-3.81 and make-4.1, and they both work for me.
2016-01-28 12:19:11 -08:00
7209c13338
Move to a regression Makefile
...
In order to have the buildbot support various types of failures it needs
to run different commands. Rather than modifying the regression script
to have a bunch of arguments I've just gone and made a makefile for
regressions instead.
This doesn't run torture right now because that's broken, but I'll add
support soon.
2016-01-26 22:50:49 -08:00
ff79a44eb0
move some utility code from uncore to junctions
2016-01-21 15:39:09 -08:00
0dc8cd5b11
move ReorderQueue and DecoupledHelper to junctions
2016-01-21 15:36:22 -08:00
fdd19145e9
bump chisel/hardfloat/junctions/uncore submodules
2016-01-17 01:50:04 -08:00
2946bc928e
Avoid muxing between bundles of different size
2016-01-16 19:01:24 -08:00
04fd407c3e
bump rocket submodule pointer
2016-01-15 15:29:23 -08:00
3b4b7126ed
Chisel3 compile-time deprecations should be runtime errors
2016-01-14 15:12:41 -08:00
33aa64212d
fix more Chisel3 deprecations
2016-01-14 15:06:30 -08:00
4ff1aea288
fix more Chisel3 deprecations
2016-01-14 14:55:45 -08:00
fc638c6339
Chisel3 compatibility fixes
2016-01-12 16:28:05 -08:00
603db5e271
Chisel3 compatibility; new NaNs; new MIPI behavior
2016-01-12 16:25:03 -08:00
0b90b8fe5f
Avoid zero-width wire case :-/
2016-01-12 15:32:29 -08:00
a953ff384a
Chisel3 compatibility: use more concrete types
2016-01-12 15:32:14 -08:00
c06884b78c
lowercase SMI to Smi
2016-01-11 17:44:10 -08:00
c81745eb8e
lowercase SMI to Smi
2016-01-11 16:18:44 -08:00
d0a14c6de9
separate TileLink converter/wrapper/unwrapper/narrower into separate file
2016-01-11 16:14:56 -08:00
8d1afa4197
bump fpga repo
2016-01-09 17:50:29 -08:00
806e40d19b
implement DMA streaming functionality
2016-01-07 19:26:15 -08:00
46069ea13b
implement streaming DMA functionality
2016-01-06 21:37:56 -08:00
2f71a3da5a
bump up submodule commits to merge commits
...
Github's PR system doesn't work so well with submodules, since it always
creates merge commits. We should probably avoid using it in the future.
2015-12-22 08:09:24 -08:00
0f51ca4c10
Merge pull request #35 from ucb-bar/dma
...
Implement DMA unit
2015-12-22 10:33:59 -05:00
09f3c5a6e3
Merge pull request #6 from ucb-bar/dma
...
Implement DMA engine
2015-12-21 13:54:38 -08:00
8190bf6e18
implement DMA unit
2015-12-16 21:27:48 -08:00
872b162e1b
implement DMA engine
2015-12-16 21:27:31 -08:00
8a61177224
generalize TwoWayCounter
2015-12-16 21:07:30 -08:00
1a272677ca
more fixes to L2 cache
2015-12-16 21:06:39 -08:00
a48237f36d
get rid of the rest of the PutBlock special casing in L2
2015-12-16 20:56:29 -08:00
560fdc19a8
add PLRU replacement option to L2 cache
2015-12-16 10:24:57 -08:00
922b1adc9c
Add optional PLRU replacement to the L2
2015-12-16 10:00:56 -08:00
7ad9deeaee
Fix issues with request merging in L2 cache and add regression tests
...
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
2015-12-15 23:02:15 -08:00
ddc79674f9
fix some issues with cache request merging
2015-12-15 21:31:02 -08:00
c080e82e92
Merge pull request #34 from seldridge/rocketchip-addons-build
...
build.scala uses space-delimited ROCKETCHIP_ADDONS
2015-12-09 11:57:19 -08:00
e50e4d4c84
build.scala uses space-delimited ROCKETCHIP_ADDONS
2015-12-09 14:17:16 -05:00
91be080526
Merge pull request #32 from ucb-bar/javamaxpermsize
...
Double Java MaxPermSize.
2015-12-07 13:58:41 -08:00
c5e9558571
Double Java MaxPermSize.
2015-12-07 12:05:06 -08:00
0c91e00676
move GroundTest configs to a separate file
2015-12-06 03:01:05 -08:00
e71293e2ae
fix bug in narrower logic
2015-12-06 02:58:12 -08:00
4f5dabcda2
add SCR file to device tree
2015-12-05 00:28:58 -08:00
6fc1e92708
add option to print cycle count regardless of exit status
2015-12-04 12:04:13 -08:00
93aa370b87
yunsup's fix for dgemm-opt assertion failure
2015-12-03 14:03:10 -08:00
f35b83d3ca
allow configuration of rocket ICache buffering
2015-12-02 17:18:39 -08:00
ebf2417a32
rocc-fpu-port merged into master for rocket
2015-12-02 09:02:43 -08:00
