6a5b2d7f59
fix assembly tests for configurations without VMU and/or user mode
2016-07-22 17:21:57 -07:00
75347eed56
some fixes and cleanup to stateless bridge
2016-07-21 19:51:26 -07:00
c31c650def
If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
2016-07-21 13:54:28 -07:00
20df74d138
generate more L1 voluntary releases in TraceGen
2016-07-21 12:33:55 -07:00
9ae23f18bd
rocket: support asynchronous external busses
2016-07-19 14:52:56 -07:00
e08ec42bc0
refactor groundtest unittests into separate package
2016-07-16 23:19:55 -07:00
407bc95c42
Rename MulDivUnroll to MulUnroll
2016-07-15 15:40:17 -07:00
4c26a6bc96
Create seperate Mul/Div paramters instead of UseFastMulDiv
2016-07-15 14:40:37 -07:00
ba08255450
bump rocket
2016-07-14 22:11:19 -07:00
768403f8fa
Bump rocket; remove ICacheBufferWays parameter
2016-07-14 12:50:16 -07:00
90bcd3dbdc
make sure DirectGroundTest testers given correct TL settings
2016-07-11 18:11:01 -07:00
8f0fa11ce4
optionally export detailed status information in DirectGroundTest
2016-07-11 18:11:00 -07:00
cb2a18b533
allow direct instatiation of arbitrary non-caching groundtests
2016-07-11 18:11:00 -07:00
f03ffb32a0
add top that directly tests the TL -> AXI converters
2016-07-11 18:11:00 -07:00
b47f8fbc41
don't use splat and bug out if too many address map entries
2016-07-11 18:10:42 -07:00
46fc9744e2
rocket: add an AXI master port into the chip
2016-07-11 12:16:44 -07:00
8ac7fa5544
ext: support multiple external AHB/AXI ports
2016-07-11 12:16:39 -07:00
9ec55ebb91
don't add io:ext region to address map if no external MMIO
2016-07-08 15:29:35 -07:00
35547aa428
allow NastiConverterTest and Memtest to run simultaneously
2016-07-08 13:40:52 -07:00
358668699f
refactoring groundtest configuration
2016-07-08 11:40:16 -07:00
eeac405ef8
get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
2016-07-08 09:33:07 -07:00
32ee5432dd
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-07 21:23:49 -07:00
8c13e78ab5
add buffering and locking to TL -> AXI converter
2016-07-06 16:57:09 -07:00
e27cb5f885
fix voluntary release issue in L2 cache
2016-07-06 16:57:01 -07:00
f79a3285fb
fix TraceGen and Nasti -> TL converter
2016-07-05 17:42:57 -07:00
c924ec2a22
fixing bufferless broadcast hub
2016-07-05 12:10:22 -07:00
b01871c3de
test configurations for both shrinking and growing TL -> MIF
2016-07-01 18:13:33 -07:00
e04e3d2571
make TestBench generator handle different top module names
2016-07-01 10:53:08 -07:00
600f2da38a
export TL interface for Mem/MMIO and fix TL width adapters
2016-06-30 18:20:43 -07:00
74cd588c65
refactor uncore to split into separate packages
2016-06-28 14:10:25 -07:00
c725a78086
Merge RTC into PRCI
2016-06-27 23:08:29 -07:00
d10fc84a8b
no longer require caching interfaces for groundtest tiles
2016-06-27 17:32:49 -07:00
2dd8d90ae4
make Comparator fit the GroundTest model
2016-06-27 16:01:32 -07:00
568bfa6c50
Purge legacy HTIF things
...
The SCR file is gone, too, because it was tightly coupled. The
general concept could be revived as a module that somehow connects
to the debug module.
2016-06-23 13:23:57 -07:00
2d44be747a
Fix groundtest without HTIF
2016-06-23 12:17:26 -07:00
30331fcaeb
Remove HTIF; use debug module for testing in simulation
2016-06-23 00:32:05 -07:00
4fbe7d6cf7
split the isa tests properly
2016-06-22 16:14:02 -07:00
3c973d429a
rename SmallConfig to WithSmallCores
2016-06-22 16:08:27 -07:00
9b9ddd0d54
get rid of leftover backup memory code
2016-06-22 16:06:41 -07:00
ff43238e6e
give DualCoreConfig L2 cache to speed up test runs
2016-06-20 17:58:26 -07:00
82169e971e
Dynamically compute number of L1 client channels
...
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.
This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
2016-06-20 13:02:31 -07:00
70d92995df
TestConfigs: add comparator config
2016-06-09 15:43:13 -07:00
1679cf4764
fix groundtest tilelink xacts
2016-06-09 15:42:44 -07:00
9e86b9efc9
Add provisional breakpoint support
2016-06-08 22:34:19 -07:00
40ab0a7960
fix TL width adapter and make it easier to switch inner data width
2016-06-08 15:38:39 -07:00
99b257316e
replace emulator with verilator for chisel3
2016-06-08 02:43:54 -07:00
2cd897e240
Revert "include the unmatched field in CDEMatchError"
...
This reverts commit ff2937a788
2016-06-07 16:13:01 -07:00
8db27a36c4
fix Tile reset power on behavior
2016-06-07 11:06:38 -07:00
5495705acf
Configs: enable AHB for FPGAs
2016-06-06 21:36:09 -07:00
ef27cc3a33
RocketChip: handle atomics only if needed
2016-06-06 21:36:03 -07:00
