riscv/rocket-chip
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Author SHA1 Message Date
Wesley W. TerpstraandGitHub 4471e0de27 Merge pull request #494 from ucb-bar/diplomatic-apb 
Diplomatic apb
 2016-12-15 17:45:20 -08:00
Wesley W. Terpstra a9b264e582 ahb: lower hsel when idle to save power 2016-12-15 15:32:30 -08:00
Wesley W. Terpstra 16febe7e94 apb: add a TileLink to APB bridge and unittest it 2016-12-15 15:32:27 -08:00
Wesley W. Terpstra ed091f55e6 apb: diplomatic APB framework 2016-12-15 13:48:50 -08:00
Wesley W. TerpstraandGitHub 4d87d07343 Merge pull request #491 from ucb-bar/ahb-hready-high 
ahb: don't violate spec with SRAM fuzzing
 2016-12-15 02:50:15 +00:00
Wesley W. Terpstra a5b8fc2317 RegisterRouterTest: start up with 0 in registers to make VIP testing easier 2016-12-14 15:38:08 -08:00
Wesley W. Terpstra 9d50704b64 ahb: don't violate spec with SRAM fuzzing 2016-12-14 15:18:41 -08:00
Wesley W. TerpstraandHenry Cook 09afbbafdb ahb: weaken RegisterRouter assertion 
As written I think it could potentially fail, but what I actually care
about is something weaker that should be true. Assert: nothing lost.
 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandHenry Cook 588b944ed4 ahb: implement and test address decoding 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandHenry Cook 5d1064fcb1 ahb: include a unit test 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandHenry Cook 51dfb9cb06 ahb: TileLink master 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandHenry Cook 01b0f6a52b ahb: new diplomacy-based AHB bus definition 2016-12-08 18:00:39 -08:00
Wesley W. TerpstraandGitHub 1bd8a2e239 Merge pull request #478 from ucb-bar/parameterize-diplomatic-connections 
Parameterize diplomatic connections
 2016-12-07 15:03:53 -08:00
Wesley W. Terpstra c2eedbfe23 tilelink2 Monitor: use Parameters instead of global variables 2016-12-07 12:24:03 -08:00
Wesley W. Terpstra 020fbe8be9 diplomacy: make config.Parameters available in bundle connect() 
This makes it posisble to use Parameters to control Monitors.
However, we need to make all LazyModules carry Parameters.
 2016-12-07 12:24:01 -08:00
Wesley W. TerpstraandHenry Cook fbfa15efea TLBroadcast: support non-FIFO devices (#482) 2016-12-05 22:10:37 -08:00
Wesley W. TerpstraandGitHub 3c9718ec8f clint: undefined registers must be zero (#480) 
This is needed so that SMP-safe boot loaders can safely
read/write to the IPI register of non-existent harts.
 2016-12-05 17:11:53 -08:00
Wesley W. Terpstra b7963eca4e copyright: ran scripts/modify-copyright 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra d4708694ea scripts/authors: Matthew Naylor's submissions were under Berkeley terms 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra e2ec1d00ad copyright: normalize /// to // in comments 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra a0e10aec05 uncore: removed obsolete Builder file 2016-11-27 22:15:43 -08:00
Wesley W. Terpstra 8510d9e697 scripts: two scripts to determine copyright holder of files 2016-11-27 22:15:38 -08:00
Wesley W. TerpstraandGitHub 4146f6a792 TLB: do not access illegal addresses (#460) 2016-11-26 15:11:42 -08:00
Wesley W. TerpstraandGitHub a17753983a coreplex: allow legacy devices to override the config string (#458) 2016-11-25 19:38:24 -08:00
Wesley W. TerpstraandGitHub 9433da8458 Merge pull request #457 from ucb-bar/jtag-depth-1 
Jtag depth 1
 2016-11-25 18:41:39 -08:00
Wesley W. Terpstra 233280e7d2 AsyncBundle: save a wasted bit when depth=1 2016-11-25 18:11:01 -08:00
Wesley W. Terpstra d755edffcc DebugTransport: use ToAsyncDebugBus for correct depth 2016-11-25 18:10:28 -08:00
Wesley W. TerpstraandGitHub 2b80386a9e rocketchip: TileInterrupts needs a TLCacheEdge (#456) 2016-11-25 17:02:29 -08:00
Wesley W. TerpstraandGitHub 1e0aca7358 dcache: the high bit of s2_req.typ is the SIGN bit (not size) (#455) 2016-11-25 15:26:22 -08:00
Wesley W. TerpstraandAndrew Waterman 0baa1c9a45 coreplex: CacheBlockOffsetBits was wrong! 
This bug is ancient. I don't understand how it never mattered before.
Anyway, in processors with a custom CacheBlockBytes, this value is wrong!
The symptom is that TL1 components end up missing high address bits.
This causes, for example, a system to jump to 0 instead of RAM.

I don't understand how this very serious bug did not cause problems before.
 2016-11-24 18:32:44 -08:00
Wesley W. Terpstra 6aeadc4551 regression: disable ComparatorL2Config for now 
This tests atomics against the L2.  However, we don't have an L2 yet so this
is hitting the broadcast hub, which does not support these operations.
 2016-11-23 20:53:36 -08:00
Wesley W. Terpstra a670f63c81 periphery: a handy trait to turn-off ExtMem 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra 30e890b480 diplomacy: include InternalNodes for AXI4 and TL 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra 9f1c668c4f config: when modifying Parameters, subordinate lookups use top 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra 566cc9e60b rocketchip: RTCPeriod config 2016-11-23 20:44:45 -08:00
Wesley W. Terpstra e87f54d4f7 rocketchip: traits for adding external TL2 ports 2016-11-23 20:44:42 -08:00
Wesley W. Terpstra 4b9dc78951 rocketchip: add a parameter-controlled debug port 2016-11-23 15:35:53 -08:00
Wesley W. Terpstra cf8ecbd53b travis: balance regression tasks a bit more fairly 2016-11-23 10:28:22 -08:00
Wesley W. Terpstra e8e95d4bcf regression: remove cde submodule update 2016-11-23 10:28:22 -08:00
Wesley W. Terpstra a93d34742a rocketchip: bump all submodules (and remove cde) 2016-11-23 10:28:22 -08:00
Wesley W. TerpstraandGitHub 612f96b2af Merge pull request #447 from ucb-bar/axi4-master 
Axi4 master
 2016-11-23 10:23:43 -08:00
Wesley W. Terpstra 1d3cad3671 tilelink2 SourceShrinker: handle degenerate cases for free 2016-11-22 22:17:30 -08:00
Wesley W. Terpstra 1e7d597fd3 rocketchip: don't waste too many sources on the AXI master port 2016-11-22 21:48:41 -08:00
Wesley W. Terpstra c0b27999ea tilelink2 SourceShrinker: a concurrency reducing adapter 2016-11-22 21:43:38 -08:00
Wesley W. Terpstra 0097274ea3 Broadcast: single-cycle response is possible 2016-11-22 20:45:40 -08:00
Wesley W. Terpstra 437be0f36a PositionalMultiQueue: use a UInt instead of Reg(Vec(Bool)) 
This results in much less Verilog to simulate
 2016-11-22 20:39:38 -08:00
Wesley W. Terpstra f9de7173cc PositionalMultiQueue: use 1-write n-read Mem instead of Reg(Vec(...)) 2016-11-22 18:46:11 -08:00
Wesley W. Terpstra d9a203b0f0 PositionalMultiQueue: convert 'next' to a single write port 2016-11-22 18:38:55 -08:00
Wesley W. Terpstra 13190a5de0 rocketchip: re-add AXI4 interface 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra c230580157 coreplex: rename RocketPlex => RocketTiles 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra bbabcf67ff coreplex: width adapter should happen as part of coherence manager 
In the future we will want the L2 to be wider on the backside so that
we can take advantage of fat DDR controllers (256bits/beat).
 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra a140b07009 rocketchip: cut coreplex from rocketchip 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra c80ee06472 rocketchip: configString is a lazy property of outer 2016-11-22 17:27:58 -08:00
Wesley W. Terpstra 3d644b943c coreplex: configString is a property of the RISCVPlatform 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra e8be365b5d rocketchip: remove GlobalAddrMap completely 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra 5fe107bb07 rocket: pass scratchpad address to block dcache 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra c18bc07bbc TLB: determine RWX from TL2 properties directly 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra 3d1a7bd6d3 travis: build verilator and toolchain as part of install 2016-11-21 21:13:26 -08:00
Wesley W. Terpstra ea3ec89676 travis: split RocketSuite into three smaller tests suites 2016-11-21 21:13:23 -08:00
Wesley W. Terpstra 1577deb324 travis: delete oldest caches; not newest 2016-11-21 21:10:29 -08:00
Wesley W. Terpstra 32a1c27441 rocket: disable nbdcache until it's fully ported 2016-11-18 19:55:24 -08:00
Wesley W. Terpstra 452bb2fc80 dcache fix TinyConfig 2016-11-18 19:50:34 -08:00
Wesley W. Terpstra d1328a6b6f rocketchip: remove most uses of GlobalAddrMap 2016-11-18 19:38:02 -08:00
Wesley W. Terpstra 001d9821bd Merge remote-tracking branch 'origin/master' into tl2-tile 2016-11-18 18:19:41 -08:00
Wesley W. Terpstra 5b594ced29 Plic: support 0 interrupts gracefully 2016-11-18 18:07:44 -08:00
Wesley W. Terpstra 13ec3853ed junctions: get unit tests running again 2016-11-18 17:38:46 -08:00
Wesley W. Terpstra 10dd6070ad groundtest: gracefully handle zero uncached ports 2016-11-18 17:26:28 -08:00
Wesley W. Terpstra 03bca77b33 tilelink2 Metadata: cannot assert data good when !valid 2016-11-18 17:16:12 -08:00
Wesley W. Terpstra be8121eeaf coreplex: fix clock crossing 2016-11-18 17:15:57 -08:00
Wesley W. Terpstra 0082d713af coreplex: disable Stateless config until we implement adapter 2016-11-18 16:23:16 -08:00
Wesley W. Terpstra 8059d33217 groundtest: simplify FancyMemtestConfig for now 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 04b9a68ea6 MergedPutRegression: wait for all Puts if tlMaxClientXacts != 3 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra cd19bf65b8 regression: fix bad regression that deadlocks SoC with illegal D stall 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 5f7fa3dae5 regression: remove illegal test which reuses the same ID 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra a6188efc41 rocketchip: break infinite Config loops 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 37a3c22639 rocketchip: move from using cde to config 2016-11-18 16:18:33 -08:00
Wesley W. Terpstra 40daea2e15 util: Config scheme supporting up with ++ 2016-11-18 16:18:30 -08:00
Wesley W. Terpstra e5febcfa33 rocketchip: there are no more useful parameters to dump 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 30425d1665 rocketchip: eliminate all Knobs 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 119ccae9af rocketchip: don't use explicit cde namespace 2016-11-18 14:31:42 -08:00
Wesley W. Terpstra 179c93db42 tilelink2 broadcast: make it controlled via Config 2016-11-17 17:26:49 -08:00
Wesley W. Terpstra f4ca5ea1f3 rocketchip: match simulated memory width to ExtMem.beatBytes 2016-11-17 15:40:47 -08:00
Wesley W. Terpstra 12d0d8bea2 rocketchip: remove obsolete bus configuration 2016-11-17 14:30:15 -08:00
Wesley W. Terpstra c82b371354 rocketchip: remove obsolete TL1 config 2016-11-17 14:24:45 -08:00
Wesley W. Terpstra dfc3a0dafb tilelink2: do not depend on obsolete TL1 configuration 2016-11-17 14:07:53 -08:00
Wesley W. Terpstra 8a0ecdaaad groundtest: ComparatorConfig lives again 2016-11-17 11:07:49 -08:00
Wesley W. Terpstra 06a7b95d0d tilelink2 broadcast: support bufferless Config 2016-11-16 12:25:11 -08:00
Wesley W. Terpstra 3703ed39f7 groundtest: PTW needs atomics 2016-11-16 12:16:54 -08:00
Wesley W. Terpstra 5d2e637a4a tilelink2 Legacy: uncached TL never needs manager_xact_id 2016-11-16 12:16:25 -08:00
Wesley W. Terpstra 10e459fedb rocket: change connection between rocketchip and coreplex 
* rtc and dtm are now crossed half-and-half on the two sides
* groundtest no longer uses riscv platform traits
 2016-11-15 18:27:52 -08:00
Wesley W. Terpstra ab3dafb8bc Monitor: restore Probe&Acquire checks 2016-11-14 15:36:52 -08:00
Wesley W. Terpstra 385b5d5698 axi4: default should be GET_EFFECTS 2016-11-14 15:19:39 -08:00
Wesley W. Terpstra 32fd11935c rocketchip: use TL2 and AXI4 for memory subsytem 2016-11-04 13:36:47 -07:00
Wesley W. TerpstraandHenry Cook 9d77e34bee tilelink2 Filter: make transfer cap robust against large filters 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook 4a2cf6431b coreplex: make 'mem' port an Option until we can use a Seq 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook 8f757a9135 coreplex: rename BankedL2 trait to BankedL2CoherenceManagers 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook b8df59f43b tilelink2 Broadcast: support "bufferless" implementation 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook 14800f8fb4 tilelink2 Broadcast: only support caching readable devices 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandHenry Cook d03046d11c coreplex: fix BankedL2 line width 2016-11-04 13:35:36 -07:00
Wesley W. TerpstraandGitHub ea602790a8 Merge pull request #432 from ucb-bar/tl2-address-filtering 
Tl2 address filtering
 2016-11-04 00:12:43 -07:00