ahb: don't violate spec with SRAM fuzzing
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@ -91,8 +91,13 @@ class AHBRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4
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val muxdata = Vec((p_mask.toBools zip (p_wdata zip d_rdata))
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map { case (m, (p, r)) => Mux(d_bypass && m, p, r) })
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// Don't fuzz hready when not in data phase
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val d_request = Reg(Bool(false))
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when (in.hready) { d_request := Bool(false) }
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when (a_request) { d_request := Bool(true) }
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// Finally, the outputs
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in.hreadyout := LFSR16(Bool(true))(0) // Bool(true)
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in.hreadyout := !d_request || LFSR16(Bool(true))(0) // Bool(true)
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in.hresp := AHBParameters.RESP_OKAY
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in.hrdata := Mux(in.hreadyout, muxdata.asUInt, UInt(0))
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}
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