riscv/rocket-chip
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Author SHA1 Message Date
Henry Cook
082b38d315 Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs. 2012-02-29 02:59:27 -08:00
Henry Cook
6304aa992f Fixed race between read resps/reps and write req/reps in null hub 2012-02-29 00:44:03 -08:00
Henry Cook
8ff6e21e3a Fixed race between read resps/reps and write req/reps in null hub 2012-02-29 00:44:03 -08:00
Andrew Waterman
eec369a1c7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Andrew Waterman
c99f6bbeb7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Henry Cook
e15284d22c Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem 2012-02-28 17:33:32 -08:00
Henry Cook
040aa9fe02 Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem 2012-02-28 17:33:32 -08:00
Daiwei Li
3f998b1353 send vcfg and setvl to vu prefetch queues 2012-02-28 14:54:48 -08:00
Henry Cook
ffc7652e01 Null coherence hub. Begin work on internal tracker logic 2012-02-27 19:10:15 -08:00
Henry Cook
5cc10337b4 Null coherence hub. Begin work on internal tracker logic 2012-02-27 19:10:15 -08:00
Andrew Waterman
7d331858e2 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman
2b1c07c723 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman
1d41a41afa remove extraneous constants 2012-02-27 17:49:48 -08:00
Yunsup Lee
3d96a2d4f0 add fpu.dec.wen := false when HAVE_FPU is turned off 2012-02-27 14:00:58 -08:00
Henry Cook
3393dc2d31 Added probe_req ready sigs, GenArray to Vec 2012-02-27 11:26:18 -08:00
Henry Cook
f0588a0052 Added probe_req ready sigs, GenArray to Vec 2012-02-27 11:26:18 -08:00
Henry Cook
70cdf869ac probe req transactors in coherence hub 2012-02-27 09:24:33 -08:00
Henry Cook
7a8f53a117 probe req transactors in coherence hub 2012-02-27 09:24:33 -08:00
Henry Cook
b6e6d603cc xact init transactors in coherence hub 2012-02-27 09:24:32 -08:00
Henry Cook
2275239f33 xact init transactors in coherence hub 2012-02-27 09:24:32 -08:00
Yunsup Lee
bfd0ae125e upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache 2012-02-26 23:46:51 -08:00
Andrew Waterman
6e706c7c74 fix yet another AMO-related replay bug 2012-02-26 20:20:45 -08:00
Andrew Waterman
e12b9eae93 remove ext_mem interface 
hindsight is 20/20
 2012-02-26 18:53:39 -08:00
Andrew Waterman
2d04664a98 simplify cpu-cache interface 2012-02-26 18:26:29 -08:00
Andrew Waterman
ad713a5d83 fix icache ram depth; new chisel 2012-02-26 17:51:46 -08:00
Yunsup Lee
f3bb02b2ea refactored dmem arbiter 2012-02-26 17:38:08 -08:00
Huy Vo
0fd777f480 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo
aa099a53fa Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo
93f41d3359 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-02-26 17:24:23 -08:00
Huy Vo
e22106af3f updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Huy Vo
5b0f7ccf68 updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Yunsup Lee
766a039ffe small changes to the dtlb arbiter 2012-02-26 16:19:50 -08:00
Daiwei Li
69260756bd change ppn and vpn in dtlb from ufix to bits 2012-02-26 02:54:31 -08:00
Yunsup Lee
49efe4b744 now vu steals cycles from the fpu's fma alu 2012-02-26 01:55:07 -08:00
Daiwei Li
47dbc2a417 head should be working again 2012-02-26 00:30:50 -08:00
Daiwei Li
569698b824 dtlb now arbitrates between cpu, vec, and vec pf 2012-02-25 22:05:30 -08:00
Yunsup Lee
ca2e70454e change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Yunsup Lee
94ba32bbd3 change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Yunsup Lee
946e0c6e4e add vector exception infrastructure 2012-02-25 16:37:56 -08:00
Yunsup Lee
3839e3a318 massive refactoring of vector constants 2012-02-25 15:55:36 -08:00
Henry Cook
8856e2b8bb More stylish bundle param names, some hub progress 2012-02-25 15:27:53 -08:00
Henry Cook
3980120279 More stylish bundle param names, some hub progress 2012-02-25 15:27:53 -08:00
Henry Cook
dfdcb7c696 Better foldR 2012-02-25 15:27:09 -08:00
Henry Cook
db6d480778 Better foldR 2012-02-25 15:27:09 -08:00
Henry Cook
b3cf8f3f35 Better abstraction of data bundles 2012-02-25 12:57:01 -08:00
Henry Cook
df97de0fd3 Better abstraction of data bundles 2012-02-25 12:57:01 -08:00
Henry Cook
4fa31b300b Added popcount util 2012-02-25 12:57:01 -08:00
Yunsup Lee
a1600d95db fix bug related to waddr and wdata in wb stage 
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
 2012-02-25 12:21:10 -08:00
Yunsup Lee
137fd62007 refactor cpfences 2012-02-25 12:20:36 -08:00
Andrew Waterman
4121fb178c clean up mul/div interface; use VU mul if HAVE_VEC 2012-02-24 19:22:35 -08:00