Better abstraction of data bundles
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4fa31b300b
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@ -4,13 +4,27 @@ import Chisel._
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import Constants._
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import hwacha.GenArray
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class HubMemReq extends Bundle {
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
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val tag = Bits(width = GLOBAL_XACT_ID_BITS)
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// Figure out which data-in port to pull from
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val data_idx = Bits(width = TILE_ID_BITS)
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val is_probe_rep = Bool()
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}
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class MemData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionInit extends Bundle {
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val ttype = Bits(width = TTYPE_BITS)
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionInitData extends MemData
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class TransactionAbort extends Bundle {
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val tileTransactionID = Bits(width = TILE_XACT_ID_BITS)
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}
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@ -27,9 +41,7 @@ class ProbeReply extends Bundle {
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class ProbeReplyData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class ProbeReplyData extends MemData
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class TransactionReply extends Bundle {
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val ttype = Bits(width = TTYPE_BITS)
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@ -37,9 +49,7 @@ class TransactionReply extends Bundle {
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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class TransactionReplyData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class TransactionReplyData extends MemData
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class TransactionFinish extends Bundle {
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val globalTransactionID = Bits(width = GLOBAL_XACT_ID_BITS)
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@ -47,6 +57,7 @@ class TransactionFinish extends Bundle {
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class ioTileLink extends Bundle {
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val xact_init = (new ioDecoupled) { new TransactionInit() }.flip
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val xact_init_data = (new ioDecoupled) { new TransactionInitData() }.flip
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val xact_abort = (new ioDecoupled) { new TransactionAbort() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
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