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rocket-chip
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More stylish bundle param names, some hub progress

This commit is contained in:
Henry Cook 2012-02-25 15:27:53 -08:00
parent db6d480778
commit 3980120279
1 changed files with 78 additions and 27 deletions
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105
rocket/src/main/scala/coherence.scala
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@ -154,23 +154,27 @@ trait FourStateCoherence extends CoherencePolicy {
class XactTracker(id: Int) extends Component {
val io = new Bundle {
val xact_init = (new ioDecoupled) { new TransactionInit() }
val probe_rep = (new ioDecoupled) { new ProbeReply() }
val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
val xact_rep = (new ioDecoupled) { new TransactionReply() }.flip
val mem_req = (new ioDecoupled) { new MemReq() }.flip
val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
val xact_finish = Bool(INPUT)
val p_rep_has_data = Bool(INPUT)
val x_init_has_data = Bool(INPUT)
val p_rep_data_idx = Bits(log2up(NTILES), INPUT)
val x_init_data_idx = Bits(log2up(NTILES), INPUT)
val rep_cnt_dec = Bits(NTILES, INPUT)
val busy = Bool(OUTPUT)
val addr = Bits(PADDR_BITS, OUTPUT)
val tile_id = Bits(TILE_ID_BITS, OUTPUT)
val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
val ttype = Bits(TTYPE_BITS, OUTPUT)
val t_type = Bits(TTYPE_BITS, OUTPUT)
val pop_p_rep = Bool(OUTPUT)
val pop_p_rep_data = Bool(OUTPUT)
val send_x_rep_ack = Bool(OUTPUT)
}
val valid = Reg(resetVal = Bool(false))
val addr = Reg{ Bits() }
val ttype = Reg{ Bits() }
val t_type = Reg{ Bits() }
val tile_id = Reg{ Bits() }
val tile_xact_id = Reg{ Bits() }
val probe_done = Reg{ Bits() }
@ -184,9 +188,9 @@ class CoherenceHubNoDir extends CoherenceHub {
def coherenceConflict(addr1: Bits, addr2: Bits): Bool = {
addr1(PADDR_BITS-1, OFFSET_BITS) === addr2(PADDR_BITS-1, OFFSET_BITS)
}
def getTransactionReplyType(ttype: UFix, count: UFix): Bits = {
def getTransactionReplyType(t_type: UFix, count: UFix): Bits = {
val ret = Wire() { Bits(width = TTYPE_BITS) }
switch (ttype) {
switch (t_type) {
is(X_READ_SHARED) { ret := Mux(count > UFix(0), X_READ_SHARED, X_READ_EXCLUSIVE) }
is(X_READ_EXCLUSIVE) { ret := X_READ_EXCLUSIVE }
is(X_READ_UNCACHED) { ret := X_READ_UNCACHED }
@ -205,17 +209,27 @@ class CoherenceHubNoDir extends CoherenceHub {
val addr_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
val tile_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
val tile_xact_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
val t_type_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
val sh_count_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
val ttype_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
val free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
val send_x_rep_ack_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
val do_free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
val p_rep_has_data_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
val p_rep_data_idx_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} }
val rep_cnt_dec_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
for( i <- 0 until NGLOBAL_XACTS) {
busy_arr.write( UFix(i), trackerList(i).io.busy)
addr_arr.write( UFix(i), trackerList(i).io.addr)
tile_id_arr.write( UFix(i), trackerList(i).io.tile_id)
tile_xact_id_arr.write(UFix(i), trackerList(i).io.tile_xact_id)
ttype_arr.write( UFix(i), trackerList(i).io.ttype)
sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
trackerList(i).io.xact_finish := free_arr.read(UFix(i))
busy_arr.write( UFix(i), trackerList(i).io.busy)
addr_arr.write( UFix(i), trackerList(i).io.addr)
tile_id_arr.write( UFix(i), trackerList(i).io.tile_id)
tile_xact_id_arr.write( UFix(i), trackerList(i).io.tile_xact_id)
t_type_arr.write( UFix(i), trackerList(i).io.t_type)
sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
send_x_rep_ack_arr.write( UFix(i), trackerList(i).io.send_x_rep_ack)
trackerList(i).io.xact_finish := do_free_arr.read(UFix(i))
trackerList(i).io.p_rep_has_data := p_rep_has_data_arr.read(UFix(i))
trackerList(i).io.p_rep_data_idx := p_rep_data_idx_arr.read(UFix(i))
trackerList(i).io.rep_cnt_dec := rep_cnt_dec_arr.read(UFix(i))
}
// Nack conflicting transaction init attempts
@ -231,14 +245,14 @@ class CoherenceHubNoDir extends CoherenceHub {
}
aborting(j) := (conflicts.orR || busy_arr.flatten().andR)
abort.valid := init.valid && aborting
abort.bits.tileTransactionID := init.bits.tileTransactionID
abort.bits.tile_xact_id := init.bits.tile_xact_id
init.ready := aborting(j) || initiating(j)
}
// Free finished transactions
for( j <- 0 until NTILES ) {
val finish = io.tiles(j).xact_finish
free_arr.write(finish.bits.globalTransactionID, finish.valid)
do_free_arr.write(finish.bits.global_xact_id, finish.valid)
finish.ready := Bool(true)
}
@ -249,18 +263,55 @@ class CoherenceHubNoDir extends CoherenceHub {
val idx = io.mem.resp_tag
val readys = Bits(width = NTILES)
for( j <- 0 until NTILES ) {
io.tiles(j).xact_rep.bits.ttype := getTransactionReplyType(ttype_arr.read(idx), sh_count_arr.read(idx))
io.tiles(j).xact_rep.bits.tileTransactionID := tile_xact_id_arr.read(idx)
io.tiles(j).xact_rep.bits.globalTransactionID := idx
io.tiles(j).xact_rep.bits.t_type := getTransactionReplyType(t_type_arr.read(idx), sh_count_arr.read(idx))
io.tiles(j).xact_rep.bits.tile_xact_id := tile_xact_id_arr.read(idx)
io.tiles(j).xact_rep.bits.global_xact_id := idx
io.tiles(j).xact_rep_data.bits.data := io.mem.resp_data
readys := Mux(xrep_cnt === UFix(0), io.tiles(j).xact_rep.ready && io.tiles(j).xact_rep_data.ready, io.tiles(j).xact_rep_data.ready)
val this_rep_valid = UFix(j) === tile_id_arr.read(idx) && io.mem.resp_val
io.tiles(j).xact_rep.valid := this_rep_valid && xrep_cnt === UFix(0)
io.tiles(j).xact_rep_data.valid := this_rep_valid
io.tiles(j).xact_rep.valid := (UFix(j) === tile_id_arr.read(idx)) && ((io.mem.resp_val && xrep_cnt === UFix(0)) || send_x_rep_ack_arr.read(idx))
io.tiles(j).xact_rep_data.valid := (UFix(j) === tile_id_arr.read(idx))
}
// If there were a ready signal due to e.g. intervening network:
// If there were a ready signal due to e.g. intervening network use:
//io.mem.resp_rdy := readys(tile_id_arr.read(idx)).xact_rep.ready
// Create an arbiter for the one memory port
// We have to arbitrate between the different trackers' memory requests
// and once we have picked a request, get the right write data
val mem_req_arb = (new Arbiter(NGLOBAL_XACTS)) { new HubMemReq() }
for( i <- 0 until NGLOBAL_XACTS ) {
mem_req_arb.io.in(i) <> trackerList(i).io.mem_req
}
mem_req_arb.io.out.ready := io.mem.req_rdy
io.mem.req_val := mem_req_arb.io.out.valid
io.mem.req_rw := mem_req_arb.io.out.bits.rw
io.mem.req_tag := mem_req_arb.io.out.bits.tag
io.mem.req_addr := mem_req_arb.io.out.bits.addr
io.mem.req_wdata := MuxLookup(mem_req_arb.io.out.bits.data_idx,
Bits(0, width = MEM_DATA_BITS),
(0 until NTILES).map( j =>
UFix(j) -> Mux(mem_req_arb.io.out.bits.is_probe_rep,
io.tiles(j).probe_rep_data.bits.data,
io.tiles(j).xact_init_data.bits.data)))
for( j <- 0 until NTILES ) {
val p_rep = io.tiles(j).probe_rep
val p_rep_data = io.tiles(j).probe_rep_data
val idx = p_rep.bits.global_xact_id
p_rep_has_data_arr.write(idx, p_rep.valid && p_rep.bits.has_data)
p_rep_data_idx_arr.write(idx, UFix(j))
p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep))(_ || _)
p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data))(_ || _)
}
for( i <- 0 until NGLOBAL_XACTS ) {
val flags = Bits(width = NTILES)
for( j <- 0 until NTILES) {
val p_rep = io.tiles(j).probe_rep
flags(j) := p_rep.valid && (p_rep.bits.global_xact_id === UFix(i))
}
rep_cnt_dec_arr.write(UFix(i), flags)
}
// Pick a single request of these types to process
//val xact_init_arb = (new Arbiter(NTILES)) { new TransactionInit() }