More stylish bundle param names, some hub progress
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db6d480778
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3980120279
@ -154,23 +154,27 @@ trait FourStateCoherence extends CoherencePolicy {
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class XactTracker(id: Int) extends Component {
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val io = new Bundle {
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val xact_init = (new ioDecoupled) { new TransactionInit() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }.flip
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val mem_req = (new ioDecoupled) { new MemReq() }.flip
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val xact_finish = Bool(INPUT)
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val p_rep_has_data = Bool(INPUT)
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val x_init_has_data = Bool(INPUT)
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val p_rep_data_idx = Bits(log2up(NTILES), INPUT)
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val x_init_data_idx = Bits(log2up(NTILES), INPUT)
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val rep_cnt_dec = Bits(NTILES, INPUT)
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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val tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
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val ttype = Bits(TTYPE_BITS, OUTPUT)
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val t_type = Bits(TTYPE_BITS, OUTPUT)
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val pop_p_rep = Bool(OUTPUT)
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val pop_p_rep_data = Bool(OUTPUT)
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val send_x_rep_ack = Bool(OUTPUT)
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}
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val valid = Reg(resetVal = Bool(false))
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val addr = Reg{ Bits() }
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val ttype = Reg{ Bits() }
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val t_type = Reg{ Bits() }
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val tile_id = Reg{ Bits() }
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val tile_xact_id = Reg{ Bits() }
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val probe_done = Reg{ Bits() }
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@ -184,9 +188,9 @@ class CoherenceHubNoDir extends CoherenceHub {
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def coherenceConflict(addr1: Bits, addr2: Bits): Bool = {
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addr1(PADDR_BITS-1, OFFSET_BITS) === addr2(PADDR_BITS-1, OFFSET_BITS)
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}
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def getTransactionReplyType(ttype: UFix, count: UFix): Bits = {
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def getTransactionReplyType(t_type: UFix, count: UFix): Bits = {
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val ret = Wire() { Bits(width = TTYPE_BITS) }
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switch (ttype) {
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switch (t_type) {
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is(X_READ_SHARED) { ret := Mux(count > UFix(0), X_READ_SHARED, X_READ_EXCLUSIVE) }
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is(X_READ_EXCLUSIVE) { ret := X_READ_EXCLUSIVE }
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is(X_READ_UNCACHED) { ret := X_READ_UNCACHED }
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@ -205,17 +209,27 @@ class CoherenceHubNoDir extends CoherenceHub {
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val addr_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val tile_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val t_type_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val sh_count_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val ttype_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val send_x_rep_ack_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val do_free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_has_data_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_data_idx_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} }
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val rep_cnt_dec_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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for( i <- 0 until NGLOBAL_XACTS) {
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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addr_arr.write( UFix(i), trackerList(i).io.addr)
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tile_id_arr.write( UFix(i), trackerList(i).io.tile_id)
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tile_xact_id_arr.write(UFix(i), trackerList(i).io.tile_xact_id)
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ttype_arr.write( UFix(i), trackerList(i).io.ttype)
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sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
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trackerList(i).io.xact_finish := free_arr.read(UFix(i))
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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addr_arr.write( UFix(i), trackerList(i).io.addr)
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tile_id_arr.write( UFix(i), trackerList(i).io.tile_id)
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tile_xact_id_arr.write( UFix(i), trackerList(i).io.tile_xact_id)
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t_type_arr.write( UFix(i), trackerList(i).io.t_type)
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sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
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send_x_rep_ack_arr.write( UFix(i), trackerList(i).io.send_x_rep_ack)
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trackerList(i).io.xact_finish := do_free_arr.read(UFix(i))
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trackerList(i).io.p_rep_has_data := p_rep_has_data_arr.read(UFix(i))
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trackerList(i).io.p_rep_data_idx := p_rep_data_idx_arr.read(UFix(i))
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trackerList(i).io.rep_cnt_dec := rep_cnt_dec_arr.read(UFix(i))
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}
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// Nack conflicting transaction init attempts
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@ -231,14 +245,14 @@ class CoherenceHubNoDir extends CoherenceHub {
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}
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aborting(j) := (conflicts.orR || busy_arr.flatten().andR)
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abort.valid := init.valid && aborting
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abort.bits.tileTransactionID := init.bits.tileTransactionID
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abort.bits.tile_xact_id := init.bits.tile_xact_id
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init.ready := aborting(j) || initiating(j)
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}
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// Free finished transactions
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for( j <- 0 until NTILES ) {
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val finish = io.tiles(j).xact_finish
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free_arr.write(finish.bits.globalTransactionID, finish.valid)
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do_free_arr.write(finish.bits.global_xact_id, finish.valid)
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finish.ready := Bool(true)
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}
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@ -249,18 +263,55 @@ class CoherenceHubNoDir extends CoherenceHub {
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val idx = io.mem.resp_tag
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val readys = Bits(width = NTILES)
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for( j <- 0 until NTILES ) {
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io.tiles(j).xact_rep.bits.ttype := getTransactionReplyType(ttype_arr.read(idx), sh_count_arr.read(idx))
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io.tiles(j).xact_rep.bits.tileTransactionID := tile_xact_id_arr.read(idx)
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io.tiles(j).xact_rep.bits.globalTransactionID := idx
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io.tiles(j).xact_rep.bits.t_type := getTransactionReplyType(t_type_arr.read(idx), sh_count_arr.read(idx))
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io.tiles(j).xact_rep.bits.tile_xact_id := tile_xact_id_arr.read(idx)
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io.tiles(j).xact_rep.bits.global_xact_id := idx
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io.tiles(j).xact_rep_data.bits.data := io.mem.resp_data
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readys := Mux(xrep_cnt === UFix(0), io.tiles(j).xact_rep.ready && io.tiles(j).xact_rep_data.ready, io.tiles(j).xact_rep_data.ready)
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val this_rep_valid = UFix(j) === tile_id_arr.read(idx) && io.mem.resp_val
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io.tiles(j).xact_rep.valid := this_rep_valid && xrep_cnt === UFix(0)
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io.tiles(j).xact_rep_data.valid := this_rep_valid
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io.tiles(j).xact_rep.valid := (UFix(j) === tile_id_arr.read(idx)) && ((io.mem.resp_val && xrep_cnt === UFix(0)) || send_x_rep_ack_arr.read(idx))
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io.tiles(j).xact_rep_data.valid := (UFix(j) === tile_id_arr.read(idx))
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}
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// If there were a ready signal due to e.g. intervening network:
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// If there were a ready signal due to e.g. intervening network use:
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//io.mem.resp_rdy := readys(tile_id_arr.read(idx)).xact_rep.ready
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// Create an arbiter for the one memory port
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// We have to arbitrate between the different trackers' memory requests
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// and once we have picked a request, get the right write data
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val mem_req_arb = (new Arbiter(NGLOBAL_XACTS)) { new HubMemReq() }
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for( i <- 0 until NGLOBAL_XACTS ) {
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mem_req_arb.io.in(i) <> trackerList(i).io.mem_req
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}
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mem_req_arb.io.out.ready := io.mem.req_rdy
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io.mem.req_val := mem_req_arb.io.out.valid
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io.mem.req_rw := mem_req_arb.io.out.bits.rw
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io.mem.req_tag := mem_req_arb.io.out.bits.tag
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io.mem.req_addr := mem_req_arb.io.out.bits.addr
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io.mem.req_wdata := MuxLookup(mem_req_arb.io.out.bits.data_idx,
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Bits(0, width = MEM_DATA_BITS),
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(0 until NTILES).map( j =>
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UFix(j) -> Mux(mem_req_arb.io.out.bits.is_probe_rep,
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io.tiles(j).probe_rep_data.bits.data,
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io.tiles(j).xact_init_data.bits.data)))
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for( j <- 0 until NTILES ) {
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val p_rep = io.tiles(j).probe_rep
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val p_rep_data = io.tiles(j).probe_rep_data
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val idx = p_rep.bits.global_xact_id
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p_rep_has_data_arr.write(idx, p_rep.valid && p_rep.bits.has_data)
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p_rep_data_idx_arr.write(idx, UFix(j))
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p_rep.ready := foldR(trackerList.map(_.io.pop_p_rep))(_ || _)
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p_rep_data.ready := foldR(trackerList.map(_.io.pop_p_rep_data))(_ || _)
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}
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for( i <- 0 until NGLOBAL_XACTS ) {
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val flags = Bits(width = NTILES)
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for( j <- 0 until NTILES) {
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val p_rep = io.tiles(j).probe_rep
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flags(j) := p_rep.valid && (p_rep.bits.global_xact_id === UFix(i))
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}
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rep_cnt_dec_arr.write(UFix(i), flags)
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}
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// Pick a single request of these types to process
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//val xact_init_arb = (new Arbiter(NTILES)) { new TransactionInit() }
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