Megan Wachs
c31c650def
If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge.
2016-07-21 13:54:28 -07:00
Howard Mao
ffe17cbb2b
bump uncore for L2 bugfix
2016-07-21 12:35:38 -07:00
Howard Mao
20df74d138
generate more L1 voluntary releases in TraceGen
2016-07-21 12:33:55 -07:00
Wesley W. Terpstra
9ae23f18bd
rocket: support asynchronous external busses
2016-07-19 14:52:56 -07:00
Howard Mao
19b44ec95b
Bug fixes in SimpleHellaCacheIF and L2 agents
...
* SimpleHellaCacheIF now properly handles both the non-blocking data
cache and blocking data cache.
* SimpleHellaCacheIF maintains ordering of replayed requests
* L2 VoluntaryReleaseTracker sends voluntary release grant properly
* Coherence protocols now downgrade for probeCopy
2016-07-19 09:35:13 -07:00
Howard Mao
39a1ecbf3c
switch groundtest to merged master
2016-07-18 09:34:27 -07:00
Howard Mao
e08ec42bc0
refactor groundtest unittests into separate package
2016-07-16 23:19:55 -07:00
Megan Wachs
407bc95c42
Rename MulDivUnroll to MulUnroll
2016-07-15 15:40:17 -07:00
Megan Wachs
4c26a6bc96
Create seperate Mul/Div paramters instead of UseFastMulDiv
2016-07-15 14:40:37 -07:00
Andrew Waterman
ba08255450
bump rocket
2016-07-14 22:11:19 -07:00
Andrew Waterman
768403f8fa
Bump rocket; remove ICacheBufferWays parameter
2016-07-14 12:50:16 -07:00
Howard Mao
18ea58c85f
remove unnecessary CAMs from converters
2016-07-13 12:42:50 -07:00
Howard Mao
4c79215fde
add a script for checking comparator trace
2016-07-12 14:42:04 -07:00
Howard Mao
90bcd3dbdc
make sure DirectGroundTest testers given correct TL settings
2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4
optionally export detailed status information in DirectGroundTest
2016-07-11 18:11:00 -07:00
Howard Mao
b64998ec05
make sure dramsim reads and writes occur in the order they are received
2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533
allow direct instatiation of arbitrary non-caching groundtests
2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0
add top that directly tests the TL -> AXI converters
2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41
don't use splat and bug out if too many address map entries
2016-07-11 18:10:42 -07:00
Wesley W. Terpstra
46fc9744e2
rocket: add an AXI master port into the chip
2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544
ext: support multiple external AHB/AXI ports
2016-07-11 12:16:39 -07:00
mwachs5
36720d915a
Update README.md ( #161 )
...
Correct typo in heading
2016-07-11 00:34:13 -07:00
Andrew Waterman
9751ea0f35
Fix Verilator VCD ( #157 )
2016-07-09 02:37:39 -07:00
Howard Mao
9ec55ebb91
don't add io:ext region to address map if no external MMIO
2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428
allow NastiConverterTest and Memtest to run simultaneously
2016-07-08 13:40:52 -07:00
Howard Mao
358668699f
refactoring groundtest configuration
2016-07-08 11:40:16 -07:00
Howard Mao
eeac405ef8
get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache
2016-07-08 09:33:07 -07:00
Andrew Waterman
32ee5432dd
Fix testing of DefaultSmallConfig; bump rocket et al
2016-07-07 21:23:49 -07:00
Howard Mao
8c13e78ab5
add buffering and locking to TL -> AXI converter
2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885
fix voluntary release issue in L2 cache
2016-07-06 16:57:01 -07:00
Andrew Waterman
2a146155fc
Update to new priv-1.9 PTE format
2016-07-06 10:15:59 -07:00
Howard Mao
f79a3285fb
fix TraceGen and Nasti -> TL converter
2016-07-05 17:42:57 -07:00
Howard Mao
c924ec2a22
fixing bufferless broadcast hub
2016-07-05 12:10:22 -07:00
Howard Mao
af51b6f363
bump groundtest and uncore
2016-07-01 18:13:46 -07:00
Howard Mao
b01871c3de
test configurations for both shrinking and growing TL -> MIF
2016-07-01 18:13:33 -07:00
Howard Mao
e04e3d2571
make TestBench generator handle different top module names
2016-07-01 10:53:08 -07:00
Howard Mao
600f2da38a
export TL interface for Mem/MMIO and fix TL width adapters
2016-06-30 18:20:43 -07:00
Howard Mao
39ec927a3f
replace complicated pattern substitutions with automatic variable
2016-06-28 18:30:11 -07:00
Howard Mao
a39a0c0ec4
.prm is output of chisel stage, not firrtl stage
2016-06-28 17:34:37 -07:00
Howard Mao
b30e0254ee
fix Makefrag to detect all Chisel source files
2016-06-28 16:39:10 -07:00
Howard Mao
ebef4ddad0
remove mention of HTIF from README
2016-06-28 15:23:32 -07:00
Andrew Waterman
f1cbb2ff77
Turn up optimization for Verilator compilation
2016-06-28 14:12:46 -07:00
Howard Mao
74cd588c65
refactor uncore to split into separate packages
2016-06-28 14:10:25 -07:00
Andrew Waterman
c725a78086
Merge RTC into PRCI
2016-06-27 23:08:29 -07:00
Howard Mao
d10fc84a8b
no longer require caching interfaces for groundtest tiles
2016-06-27 17:32:49 -07:00
Howard Mao
2dd8d90ae4
make Comparator fit the GroundTest model
2016-06-27 16:01:32 -07:00
Howard Mao
800e62412a
use the fast version of asm/bmark-tests
2016-06-24 15:36:10 -07:00
Howard Mao
d6ba0437ff
merge different configs into regression suites to reduce travis build times
2016-06-24 13:02:29 -07:00
Andrew Waterman
87a4858aa6
Exit from testbench, not C code
...
Otherwise, we don't get coverage data from the simulator.
2016-06-23 20:54:07 -07:00
Howard Mao
4cd709c516
fix Comparator in groundtest
2016-06-23 15:47:24 -07:00
