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Commit Graph

43 Commits

Author SHA1 Message Date
7b20609d4d reorganize moving non-submodule packages into src/main/scala 2016-08-19 13:45:23 -07:00
ed827678ac Write test harness in Chisel
This is an unavoidably invasive commit, because it affects the unit tests
(which formerly exited using stop()), the test harness Verilog generator
(since it is no longer necessary), and the DRAM model (since it is no
longer connected).  However, this should substantially reduce the effort
of building test harnesses in the future, since manual or semi-automatic
Verilog writing should no longer be necessary.  Furthermore, there is now
very little duplication of effort between the Verilator and VCS test
harnesses.

This commit removes support for DRAMsim, which is a bit of an unfortunate
consequence.  The main blocker is the lack of Verilog parameterization for
BlackBox.  It would be straightforward to revive DRAMsim once support for
that feature is added to Chisel and FIRRTL.  But that might not even be
necessary, as we move towards synthesizable DRAM models and FAME-1
transformations.
2016-08-15 23:27:27 -07:00
fb476d193c refactor main App for better code re-use 2016-08-11 16:15:23 -07:00
647dbefd9b split coreplex off into separate package 2016-08-10 18:04:22 -07:00
2a5aeeae24 add sbt pack plugin (#197) 2016-08-08 19:31:03 -07:00
cc635c386f Make Chisel3 the default version for SBT 2016-07-29 17:56:42 -07:00
2c17f828b6 bump chisel and rocket 2016-06-06 21:36:51 -07:00
a8462d3cfc bump chisel 2016-05-25 11:09:50 -07:00
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
cd9e07d8e7 Update sbt to 0.13.11 2016-04-01 18:18:08 -07:00
cddfdf0929 Add CHISEL_VERSION make argument
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
476db6ef39 Move to a newer Scala version
Chisel3 needs a newer version of Scala to run correctly.
2016-03-24 12:00:13 -07:00
e50e4d4c84 build.scala uses space-delimited ROCKETCHIP_ADDONS 2015-12-09 14:17:16 -05:00
55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
fd58c52250 Update to latest chisel 2015-09-20 13:37:53 -07:00
9b038db34a Upgrade scala to 2.11.6 2015-08-05 15:37:03 -07:00
51c42083d0 Add new junctions repo as submodule (contains externally facing buses and peripherals).
Bump all submodules.
2015-07-29 18:15:45 -07:00
bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS 2015-07-22 11:49:10 -07:00
09e29e8fe0 add zscale
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo.
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
fefa560017 Change addons subproject to use .addons-dont-touch directory instead of addons
This hides the directory name under standard invocations of ls and thus avoids confusing the user with extra directory names.
2014-09-25 06:46:06 -07:00
69d765744c Adjustments to the build structure (see below)
All 'addon' subprojects now have their sources aggregated into the addons subproject. This is done via a source copy (so that sbt will only rebuild sources that actually changed). To prevent caching issues the addons/src directory is CLEARED and then refilled every time addons is compiled. Thus, it is CRUCIAL NO SOURCES ARE MANUALLY ADDED TO addons/src AS THEY WILL BE WIPED BY addons/prepare. Due to sbt source caching, sbt will still be able to tell which sources have changed. (Strangely, sbt would not cache sources in extra unmanaged source directories and thus would always recompile them.) Also, cleaned up project/build.scala a bit to remove some warnings: Added import scala.language/postFixOps (so make! at the bottom no longer errors) and .toURI.toURL (as straight .toURL has been deprecated by the java standard library).
2014-09-25 06:45:21 -07:00
3b9624277a normalize rocket-chip to reference-chip 2014-09-25 06:45:09 -07:00
2367b7beb5 Added logic to sbt so that, for rocketchip, it will automatically include src/main/scala sources from subdirectories into the rocketchip top-level project not already handled by formal subprojects 2014-09-12 01:08:11 -07:00
2c33852c52 final touches 2014-09-12 00:19:29 -07:00
c03c09ec31 update for rocket-chip release 2014-08-31 20:26:55 -07:00
e4b56b5d0e generate verilog for rekall 2014-03-15 15:31:04 -07:00
5128298e8a allow chisel to elaborate Modules outside of the ReferenceChip package 2014-02-05 03:29:23 -08:00
e50c5180cd Merge branch 'master' into hwacha 2013-11-14 16:03:55 -08:00
c137cf1a46 Added line to fix race condition in sbt compile; fixed .gitignores 2013-11-08 15:30:08 -08:00
7da65434ee Initial commit for the hwacha reference-chip/rocket re-integration. 2013-10-30 20:44:02 -07:00
3c1d1f7981 Fix(?) SBT race by defining subproject build order 2013-10-29 13:27:36 -07:00
fc9c676fc1 add chisel and hardfloat back as sub-projects, bump other sub-projects 2013-09-26 12:01:46 -07:00
69daae0dae Add dependency resolvers to build.scala to fix build script 2013-09-05 14:56:41 -07:00
b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes 2013-08-19 19:54:41 -07:00
4d916b56e3 Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file. 2013-07-24 23:28:43 -07:00
7330deb13a print stack trace if elaboration fails 2012-11-20 05:39:48 -08:00
7bcf59a18f support continous compilation via "make test"
for c++ emulator only, for now
2012-11-17 19:58:18 -08:00
538b23c223 Initial version of using sbt tasks to elaborate chisel source and invoke backends' makefiles 2012-10-23 12:52:59 -07:00
17d2bd8926 Initial version of sbt tasks (elaborate task with no parameters) 2012-10-23 12:52:00 -07:00
24a49350cc reference chip design 2012-10-09 13:05:56 -07:00
93a0182b96 everything to get emulator working 2012-10-01 19:30:11 -07:00