riscv/rocket-chip
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Massive update containing several months of changes from the now-defunct private chip repo.

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* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
This commit is contained in:
Henry Cook
2015-06-25 23:17:35 -07:00
parent 12d8d8c5e3
commit d3ccec1044
19 changed files with 697 additions and 398 deletions
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project/plugins.sbt Normal file
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resolvers += "jgit-repo" at "http://download.eclipse.org/jgit/maven"
addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.5.3")
addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "0.8.1")