Yunsup Lee
|
3c3c946755
|
move to new version of hardfloat
|
2015-11-14 14:49:17 -08:00 |
|
Howard Mao
|
e12efab423
|
skip meta_write state if no meta write pending
|
2015-11-13 13:50:35 -08:00 |
|
Yunsup Lee
|
608e4b2851
|
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
|
2015-11-12 20:44:25 -08:00 |
|
Howard Mao
|
a1063bad54
|
fix issues with non-allocating put/get
|
2015-11-12 15:54:34 -08:00 |
|
Howard Mao
|
19daee10f0
|
use default constructors for IOMSHR acquire construction
|
2015-11-12 15:54:05 -08:00 |
|
Howard Mao
|
7e7d688a01
|
make sure L2 passes no-alloc acquires through to outer memory
|
2015-11-12 15:40:58 -08:00 |
|
Howard Mao
|
b3865c370a
|
make sure correct addr_beat is sent for Get response by narrower/converter
|
2015-11-12 15:40:38 -08:00 |
|
Howard Mao
|
f397d61033
|
add alloc option to Put constructor
|
2015-11-12 11:39:59 -08:00 |
|
Howard Mao
|
7733fbe6a3
|
make sure no-alloc write still updates data array if there is a cache hit
|
2015-11-12 11:39:36 -08:00 |
|
Howard Mao
|
10f4c6c71c
|
interleave cached and uncached requests
|
2015-11-12 11:34:44 -08:00 |
|
Colin Schmidt
|
97d0e195ae
|
Merge pull request #28 from ucb-bar/yusnup
Don't re-generate the .d files on "make clean"
|
2015-11-12 00:46:21 -08:00 |
|
Palmer Dabbelt
|
07f0e6be94
|
Don't re-generate the .d files on "make clean"
|
2015-11-12 00:41:55 -08:00 |
|
Howard Mao
|
7cae6cedf5
|
finished bit should be set true if generator not being used
|
2015-11-11 18:51:16 -08:00 |
|
Howard Mao
|
f93872d6b4
|
make sure cached generator actually drives finished signal
|
2015-11-11 18:45:36 -08:00 |
|
Howard Mao
|
eeda3dd770
|
add README
|
2015-11-11 18:30:19 -08:00 |
|
Howard Mao
|
9482d944ca
|
make Uncached generator vary the alloc bit
|
2015-11-11 18:26:56 -08:00 |
|
Howard Mao
|
6ddf81090b
|
didn't mean to turn off GenerateCached in last commit
|
2015-11-11 17:39:08 -08:00 |
|
Howard Mao
|
11f0b3d8db
|
restore old L2 cache AcquireTransactor configuration
|
2015-11-11 17:10:58 -08:00 |
|
Howard Mao
|
31da692ccc
|
default to single tile in WithMemtest
|
2015-11-11 14:54:13 -08:00 |
|
Howard Mao
|
55581195eb
|
add groundtest submodule for simple memory testing
|
2015-11-11 14:33:02 -08:00 |
|
Howard Mao
|
8a6b231b08
|
explicitly configure the number of requests being sent by generators
|
2015-11-11 14:32:19 -08:00 |
|
Howard Mao
|
149480411e
|
make sure ClientTileLinkEnqueuer uses the correct parameters
|
2015-11-10 16:09:19 -08:00 |
|
Howard Mao
|
b59ce5fed4
|
make sure L2 waits for outer grant before sending grant for write request
|
2015-11-10 16:06:14 -08:00 |
|
Howard Mao
|
13f62e0364
|
make sure generators can detect lockup
|
2015-11-10 14:39:56 -08:00 |
|
Howard Mao
|
520925c207
|
fix up build.sbt and add gitignore
|
2015-11-10 13:38:39 -08:00 |
|
Howard Mao
|
51f128ec74
|
actually use backendBuffering in front of unwrapper/converter chain
|
2015-11-09 11:50:18 -08:00 |
|
Howard Mao
|
42d3d09d7a
|
add a ClientTileLinkEnqueuer to complement the TileLinkEnqueuer
|
2015-11-09 11:49:19 -08:00 |
|
Howard Mao
|
7942be4e01
|
make sure outerTL method is idempotent
|
2015-11-09 11:10:02 -08:00 |
|
Andrew Waterman
|
59ca373146
|
Merge pull request #18 from jackkoenig/master
Fix SimpleHellaCacheIF assumption about receiving rejected request ba…
|
2015-11-08 22:38:01 -08:00 |
|
jackkoenig
|
1e259a55da
|
Fix SimpleHellaCacheIF assumption about receiving rejected request back 2 cycles later
|
2015-11-08 21:16:31 -08:00 |
|
Yunsup Lee
|
df5daaa72e
|
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
|
2015-11-06 23:57:42 -08:00 |
|
Andrew Waterman
|
2f515b2af6
|
Reduce critical path for fdiv valid signal
|
2015-11-06 23:28:31 -08:00 |
|
Henry Cook
|
e3efc09b5b
|
remove unnecessary UInt encode/decode on releaseMatches path
|
2015-11-05 17:20:03 -08:00 |
|
Yunsup Lee
|
1e772daeea
|
no spaces in Makefrag
|
2015-11-05 16:42:05 -08:00 |
|
Howard Mao
|
cb0c2df051
|
update fpga-zynq
|
2015-11-05 10:50:13 -08:00 |
|
Howard Mao
|
42e7067400
|
bump uncore
|
2015-11-05 10:49:25 -08:00 |
|
Howard Mao
|
bbf14ddc01
|
use definitions in consts header whenever possible
|
2015-11-05 10:48:32 -08:00 |
|
Howard Mao
|
fb501e75c0
|
fixes for sub-block TL requests in uncore
|
2015-11-05 10:48:32 -08:00 |
|
Howard Mao
|
7b252d8f89
|
get rid of now-unnecessary bits in MIF tag
|
2015-11-05 10:48:32 -08:00 |
|
Howard Mao
|
ba5a6af05c
|
correctly stripe data across memory channels in simulation
|
2015-11-05 10:48:32 -08:00 |
|
Sagar Karandikar
|
ee9195be26
|
rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity
|
2015-11-05 10:48:32 -08:00 |
|
Sagar Karandikar
|
354abf5e6b
|
fix NSets calculation
|
2015-11-05 10:48:32 -08:00 |
|
Howard Mao
|
dcef020ca0
|
get multichannel simulation working in emulator
|
2015-11-05 10:48:32 -08:00 |
|
Howard Mao
|
04d92dddbd
|
add back decoupled NASTI connection at edge of RocketChip
|
2015-11-05 10:48:32 -08:00 |
|
Yunsup Lee
|
51116e0674
|
add 2 and 4 memory channel configs
|
2015-11-05 10:48:32 -08:00 |
|
Yunsup Lee
|
0d245741bc
|
add multichannel NASTI support in Verilog testbench
|
2015-11-05 10:48:32 -08:00 |
|
Howard Mao
|
9dabcab9c2
|
Get rid of MemIO in Top and replace with AXI throughout
|
2015-11-05 10:48:32 -08:00 |
|
Henry Cook
|
3698153535
|
OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank
|
2015-11-03 14:31:35 -08:00 |
|
Howard Mao
|
3e906c8620
|
shave off channel select bits in MultiChannel router
|
2015-11-02 22:39:50 -08:00 |
|
Howard Mao
|
baa2544651
|
Fix some more issues with narrower
|
2015-10-31 19:36:30 -07:00 |
|