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2979 Commits

Author SHA1 Message Date
Howard Mao b7723f1ff8 make unit tests local to the packages being tested 2016-08-01 17:02:00 -07:00
Howard Mao 98eede0505 some refactoring in RocketChip top-level 2016-08-01 17:02:00 -07:00
Megan Wachs 55c992bb3a Use FoldRight() instead of for loop 2016-08-01 16:56:33 -07:00
Megan Wachs 8db2e8829f Allow aggregate CONFIG on Command Line 2016-08-01 14:24:16 -07:00
Andrew Waterman fe670e5421 Stop using deprecated FileSystemUtilities to create files 2016-07-31 18:04:56 -07:00
Andrew Waterman 832e56d3c7 Fix toBits/toUInt/toSInt deprecation warnings 2016-07-31 17:13:52 -07:00
Andrew Waterman a6e009d8de [rocket] Fix frontend mask when fetchWidth == 1 2016-07-31 15:21:17 -07:00
Andrew Waterman c49dad2e9d Improve PTW QoR 2016-07-29 17:56:42 -07:00
Andrew Waterman cc635c386f Make Chisel3 the default version for SBT 2016-07-29 17:56:42 -07:00
mwachs5 4465260469 Update README.md
- List things that are no longer submodules as subpackages instead
- clean up some formatting issues
2016-07-29 17:56:42 -07:00
Andrew Waterman 058396aefe [rocket] Implement RVC 2016-07-29 17:56:42 -07:00
Andrew Waterman c465120610 [rocket] use more standard pattern for computing integer min 2016-07-29 17:56:42 -07:00
Andrew Waterman ffac86b041 [rocket] only write badaddr on certain exceptions 2016-07-29 17:56:42 -07:00
Andrew Waterman 0d3d9fca25 [rocket] Allow zapping of BTB entries
This is necessary to guarantee forward progress with RVC, since if the
BTB keeps mispredicting, the processor might never successfully
fetch both halves of a misaligned instruction.
2016-07-29 17:56:42 -07:00
Andrew Waterman 8e0392f24b [rocket] don't hard-code instruction width in BHT 2016-07-29 17:56:42 -07:00
Howard Mao f34b0b0447 make sure L2 tracker doesn't read data array again if data buffer already filled 2016-07-29 16:47:31 -07:00
Howard Mao 2891eb879a add MergedPutRegression to uncover merged put after release bug in L2 2016-07-29 16:42:28 -07:00
Howard Mao 064020bdd7 make sure Memtest generators write different data to each address 2016-07-29 14:22:46 -07:00
Howard Mao 5a3beca097 add RepeatedGetRegression to uncover L2 merged get miss bug 2016-07-28 19:58:47 -07:00
Howard Mao cb86aaa46b fix trace generator addresses 2016-07-28 17:56:14 -07:00
Andrew Waterman 8a7fc75b53 fix metadata race in blocking L1 DCache 2016-07-28 17:54:28 -07:00
Howard Mao bd5972503f move groundtest/scripts to top-level scripts/ 2016-07-28 11:36:55 -07:00
Howard Mao 478f494626 Merge remote-tracking branch 'groundtest/master' into mono-repo 2016-07-28 11:28:06 -07:00
Howard Mao a5b88d0bdc Merge remote-tracking branch 'junctions/master' into mono-repo 2016-07-28 11:27:47 -07:00
Howard Mao 373fd427dc Merge remote-tracking branch 'rocket/master' into mono-repo 2016-07-28 11:27:29 -07:00
Howard Mao ce242b8f3f Merge remote-tracking branch 'uncore/master' into mono-repo 2016-07-28 11:23:31 -07:00
Howard Mao aefba04fb3 get rid of submodules in preparation for merging 2016-07-28 11:21:08 -07:00
Howard Mao 6de2a3e3b1 get rid of fpga-zynq submodule 2016-07-28 11:07:47 -07:00
Howard Mao fe51a35fa9 a few more submodule bumps 2016-07-28 09:25:59 -07:00
Howard Mao bf35f980a6 make sure PTE cache is power of 2 in size to satisfy PseudoLRU requirement 2016-07-27 18:40:38 -07:00
Howard Mao fbcc7317cf make sure PseudoLRU is given power of 2 ways 2016-07-27 18:39:33 -07:00
Howard Mao 15d1aa9346 make sure TrackerAllocationIO addr_block has correct direction set 2016-07-27 16:47:22 -07:00
Howard Mao 9c89290efc fix LRSC issue (fixes issue #86) 2016-07-26 22:25:04 -07:00
Howard Mao 0bd7ef1278 re-enable SCs inflight with other requests 2016-07-26 22:21:41 -07:00
Howard Mao df07771fa0 add uncached noise generator to TraceGen 2016-07-26 22:21:10 -07:00
Howard Mao dcfcac9530 fix LRSC issue (RocketChip issue #86)
It was possible that the result of a store-conditional could get lost if it
did not depend on the result of the corresponding load-reserved.

This was because the MSHR does not update the client state based on the
secondary requests. So the LR would acquire the line in clientExcusiveClean,
but then we would fail to update the metadata array to change the state
to clientExclusiveDirty.

The solution is to track whether a secondary acquire would cause the
line to be dirty. If so, use M_XWR instead of the primary command to
generate the update coherence state.
2016-07-26 18:41:52 -07:00
Howard Mao ecd1af326c fix L2 deadlock bug and add more advanced trace generator 2016-07-26 12:43:08 -07:00
Howard Mao 82bbbf908d Fix L2 Writeback deadlock issue
The deadlock condition occurs when the acquire tracker attempts to
request a writeback while the writeback unit is still busy and a
voluntary release for the block to be written back is coming in.

The voluntary release cannot be accepted because it conflicts with the
acquire tracker. The acquire tracker can't merge the voluntary release
because it is waiting to send the writeback. The writeback can't
progress because the release it is waiting on is behind the voluntary
release.

The solution to this is to break the atomicity guarantee between the
acquire tracker and the writeback unit. This allows the voluntary
release tracker to take the voluntary release before the writeback unit
accepts the conflicting request. This causes a potential race condition
for the metadata array. The solution to this is to have the writeback
unit re-read the metadata after accepting a request.
2016-07-26 12:31:08 -07:00
Howard Mao 1063d90993 make sure L1 and L2 agree on coherence policy 2016-07-25 12:20:49 -07:00
Howard Mao 6a5b2d7f59 fix assembly tests for configurations without VMU and/or user mode 2016-07-22 17:21:57 -07:00
Wesley W. Terpstra 11ec5b2cf4 bram: don't deal with multibeat; rely on the fragmenter 2016-07-22 14:51:05 -07:00
Wesley W. Terpstra a52d418439 fragmenter: support multi-beat get/put via fragmenting to single-beat operations 2016-07-22 14:48:22 -07:00
Howard Mao 51edd19e85 add U bit to misa register 2016-07-22 14:22:59 -07:00
Howard Mao 75347eed56 some fixes and cleanup to stateless bridge 2016-07-21 19:51:26 -07:00
Howard Mao 9168f35971 clean up the requirements in StatelessBridge
* No need to check that release ID bits and acquire ID bits the same
 * Check that inner and outer coherence policies match
2016-07-21 19:41:56 -07:00
Colin Schmidt a43ad522dc add clock override to tile constructor (#42)
useful to have upstream so that tape-outs can construct
rocket-chip to have cores on different clocks without
forking rocket
2016-07-21 17:56:52 -07:00
Howard Mao 12067a3b8d make sure outer probe and finish lines are disconnected 2016-07-21 15:15:44 -07:00
Howard Mao c38dff0855 add some more warnings about the StatelessBridge 2016-07-21 15:07:10 -07:00
Megan Wachs c31c650def If NTiles == 1, only use MEI. Also Create configuration for ManagerToClientStatelessBridge. 2016-07-21 13:54:28 -07:00
Megan Wachs eb9e998c08 Add ManagerToClientStatelessBridge 2016-07-21 13:49:16 -07:00