riscv/rocket-chip
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489 Commits

Author SHA1 Message Date
Andrew Waterman
ba08255450 bump rocket 2016-07-14 22:11:19 -07:00
Andrew Waterman
768403f8fa Bump rocket; remove ICacheBufferWays parameter 2016-07-14 12:50:16 -07:00
Howard Mao
90bcd3dbdc make sure DirectGroundTest testers given correct TL settings 2016-07-11 18:11:01 -07:00
Howard Mao
8f0fa11ce4 optionally export detailed status information in DirectGroundTest 2016-07-11 18:11:00 -07:00
Howard Mao
cb2a18b533 allow direct instatiation of arbitrary non-caching groundtests 2016-07-11 18:11:00 -07:00
Howard Mao
f03ffb32a0 add top that directly tests the TL -> AXI converters 2016-07-11 18:11:00 -07:00
Howard Mao
b47f8fbc41 don't use splat and bug out if too many address map entries 2016-07-11 18:10:42 -07:00
Wesley W. Terpstra
46fc9744e2 rocket: add an AXI master port into the chip 2016-07-11 12:16:44 -07:00
Wesley W. Terpstra
8ac7fa5544 ext: support multiple external AHB/AXI ports 2016-07-11 12:16:39 -07:00
Howard Mao
9ec55ebb91 don't add io:ext region to address map if no external MMIO 2016-07-08 15:29:35 -07:00
Howard Mao
35547aa428 allow NastiConverterTest and Memtest to run simultaneously 2016-07-08 13:40:52 -07:00
Howard Mao
358668699f refactoring groundtest configuration 2016-07-08 11:40:16 -07:00
Howard Mao
eeac405ef8 get rid of TL -> AXI buffering and fix SimpleHellaCacheIF for non-blocking DCache 2016-07-08 09:33:07 -07:00
Andrew Waterman
32ee5432dd Fix testing of DefaultSmallConfig; bump rocket et al 2016-07-07 21:23:49 -07:00
Howard Mao
8c13e78ab5 add buffering and locking to TL -> AXI converter 2016-07-06 16:57:09 -07:00
Howard Mao
e27cb5f885 fix voluntary release issue in L2 cache 2016-07-06 16:57:01 -07:00
Howard Mao
f79a3285fb fix TraceGen and Nasti -> TL converter 2016-07-05 17:42:57 -07:00
Howard Mao
c924ec2a22 fixing bufferless broadcast hub 2016-07-05 12:10:22 -07:00
Howard Mao
b01871c3de test configurations for both shrinking and growing TL -> MIF 2016-07-01 18:13:33 -07:00
Howard Mao
e04e3d2571 make TestBench generator handle different top module names 2016-07-01 10:53:08 -07:00
Howard Mao
600f2da38a export TL interface for Mem/MMIO and fix TL width adapters 2016-06-30 18:20:43 -07:00
Howard Mao
74cd588c65 refactor uncore to split into separate packages 2016-06-28 14:10:25 -07:00
Andrew Waterman
c725a78086 Merge RTC into PRCI 2016-06-27 23:08:29 -07:00
Howard Mao
d10fc84a8b no longer require caching interfaces for groundtest tiles 2016-06-27 17:32:49 -07:00
Howard Mao
2dd8d90ae4 make Comparator fit the GroundTest model 2016-06-27 16:01:32 -07:00
Andrew Waterman
568bfa6c50 Purge legacy HTIF things 
The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.
 2016-06-23 13:23:57 -07:00
Andrew Waterman
2d44be747a Fix groundtest without HTIF 2016-06-23 12:17:26 -07:00
Andrew Waterman
30331fcaeb Remove HTIF; use debug module for testing in simulation 2016-06-23 00:32:05 -07:00
Howard Mao
4fbe7d6cf7 split the isa tests properly 2016-06-22 16:14:02 -07:00
Howard Mao
3c973d429a rename SmallConfig to WithSmallCores 2016-06-22 16:08:27 -07:00
Howard Mao
9b9ddd0d54 get rid of leftover backup memory code 2016-06-22 16:06:41 -07:00
Howard Mao
ff43238e6e give DualCoreConfig L2 cache to speed up test runs 2016-06-20 17:58:26 -07:00
Howard Mao
82169e971e Dynamically compute number of L1 client channels 
Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
 2016-06-20 13:02:31 -07:00
Wesley W. Terpstra
70d92995df TestConfigs: add comparator config 2016-06-09 15:43:13 -07:00
Howard Mao
1679cf4764 fix groundtest tilelink xacts 2016-06-09 15:42:44 -07:00
Andrew Waterman
9e86b9efc9 Add provisional breakpoint support 2016-06-08 22:34:19 -07:00
Howard Mao
40ab0a7960 fix TL width adapter and make it easier to switch inner data width 2016-06-08 15:38:39 -07:00
Donggyu Kim
99b257316e replace emulator with verilator for chisel3 2016-06-08 02:43:54 -07:00
Howard Mao
2cd897e240 Revert "include the unmatched field in CDEMatchError" 
This reverts commit ff2937a788.
 2016-06-07 16:13:01 -07:00
Howard Mao
8db27a36c4 fix Tile reset power on behavior 2016-06-07 11:06:38 -07:00
Wesley W. Terpstra
5495705acf Configs: enable AHB for FPGAs 2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33 RocketChip: handle atomics only if needed 2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf RocketChip: add ahb mem interface 2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2 RocketChip: rename mem to mem_axi in preparation for new bus type 2016-06-06 21:35:55 -07:00
Wesley W. Terpstra
2086c0d603 Configs: add a parameter to control the memory subsystem interface 2016-06-06 21:35:43 -07:00
Wesley W. Terpstra
2ddada1732 ahb: add mmio_ahb option 2016-06-06 21:35:39 -07:00
Wesley W. Terpstra
31f1dcaf84 ahb: rename mmio outputs to mmio_axi 2016-06-06 21:35:34 -07:00
Wesley W. Terpstra
7a24527448 ahb: make MMIO channels specifiy bus type (we will have more than one bridge) 2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b ahb: AHB parameters should be site specific 
Conflicts:
	src/main/scala/Configs.scala
 2016-06-06 21:35:24 -07:00
Howard Mao
ff2937a788 include the unmatched field in CDEMatchError 2016-06-06 11:23:20 -07:00
Andrew Waterman
d24c87f8ba Update PLIC/PRCI address map (#124) 2016-06-06 04:51:55 -07:00
Andrew Waterman
ece3ab9c3d Refactor AddrMap and its usage (#122) 2016-06-03 17:29:05 -07:00
Andrew Waterman
c8338ad809 Instantiate Debug Module (#119) 2016-06-02 10:53:41 -07:00
Andrew Waterman
44a216038f Use more generic TileLinkWidthAdapter 2016-05-27 13:38:13 -07:00
Andrew Waterman
10f0e13c25 Use more parsimonious queue depths 2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4 By default, use same TileLink width everywhere 
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
 2016-05-26 18:04:01 -07:00
Wesley W. Terpstra
976d4d3184 ahb: AHB parameters should match TileLink parameters by default 
Closes #116
 2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010 Support M-mode-only implementations 2016-05-25 15:40:53 -07:00
Andrew Waterman
e82c080c3c Add blocking D$ 2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5 remove zscale 2016-05-19 09:43:15 -07:00
Colin Schmidt
abb0e2921b return non-zero exit codes when an assertion fires 
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
 2016-05-18 12:57:58 -07:00
Andrew Waterman
684d902059 Fix PLIC instantiation when S-mode is disabled 2016-05-13 11:22:46 -07:00
Andrew Waterman
6aa708bcee Disable MMIO by default to avoid disconnected nets 2016-05-11 13:12:39 -07:00
Andrew Waterman
aac89ca1f0 Add PLIC 2016-05-10 00:27:31 -07:00
Howard Mao
df479d7935 don't make MIFTagBits a computed parameter 2016-05-08 11:04:58 -07:00
Howard Mao
3b0e9167fa add AXI to AHB converter and more conformant HASTI RAM 2016-05-06 11:32:03 -07:00
Howard Mao
dfcb73b6c9 groundtest only needs to write to a single tohost 2016-05-03 20:21:13 -07:00
Howard Mao
4045a07eda Remove need for separate riscv-tests for groundtest 2016-05-03 18:29:46 -07:00
Howard Mao
8f891437b5 fix CacheFillTest 2016-05-03 14:57:05 -07:00
Andrew Waterman
15f4af19cf Remove HTIF CPU port 2016-05-03 13:55:59 -07:00
Howard Mao
487d0b356e fixes to get groundtest working with priv-1.9 changes 2016-05-03 13:09:44 -07:00
Andrew Waterman
c7c8ae5468 Instantiate PRCI block 2016-05-02 18:08:33 -07:00
Andrew Waterman
6d1e82bddf Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port 2016-05-02 15:21:55 -07:00
Andrew Waterman
c4d2d29e80 Stub out debug module, rather than leaving it floating 2016-04-30 22:37:39 -07:00
Andrew Waterman
46bbbba5e6 New address map 2016-04-30 20:59:36 -07:00
Andrew Waterman
d0aa4c722d More WIP on new memory map 2016-04-28 16:15:31 -07:00
Andrew Waterman
1f211b37df WIP on new memory map 2016-04-27 14:57:54 -07:00
Colin Schmidt
48170fd9aa add default cases to configs that use CDEMatchError 
this avoids filling in the stack trace every time
a config doesn't contain the parameter
 2016-04-22 12:14:58 -07:00
Howard Mao
f7af908969 put memory into the address map and no longer use MMIOBase 2016-04-21 18:53:16 -07:00
Howard Mao
c5838dd9b3 Fix narrow read/write behavior for AXI converters and fix L2 bugs 
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.

There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.

There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
 2016-04-12 15:39:15 -07:00
Andrew Waterman
b43a85e2e8 Make ExampleSmallConfig/DefaultRV32Config smaller 2016-04-01 18:18:08 -07:00
Andrew Waterman
6878e3265f Default RowBits to TileLink width, not XLen 2016-04-01 18:18:08 -07:00
Henry Cook
35d02c5096 LRSC fix. RocketChipNetwork moved to uncore. 2016-04-01 18:09:00 -07:00
Howard Mao
4f06a5ff6b add memtest config for testing memory channel mux 2016-03-31 18:41:56 -07:00
Howard Mao
5a74a9b1e7 switch memory interconnect from AXI to TileLink 2016-03-31 18:18:30 -07:00
Howard Mao
7c3b57b8fa switch MMIO network to TileLink 2016-03-31 14:30:10 -07:00
Howard Mao
c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
Howard Mao
1e03408323 get rid of mt benchmark suite 2016-03-29 20:16:07 -07:00
Howard Mao
ad93e0226d Changes to prepare for switch to TileLink interconnect 
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
 2016-03-29 20:16:07 -07:00
jackkoenig
5378f79b50 Bump chisel3 and firrtl, add support for firrtl $ delimiter 2016-03-29 20:16:07 -07:00
Howard Mao
9b9c662952 fix w_last wire 2016-03-29 20:16:07 -07:00
Howard Mao
e1a03cc9ac fix issue with partial writemasks 2016-03-29 20:16:07 -07:00
Andrew Waterman
6c48dc3471 Use more sensible knob values for SmallConfig 2016-03-25 14:18:24 -07:00
Palmer Dabbelt
cddfdf0929 Add CHISEL_VERSION make argument 
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3.  Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
d697559754 Correct the polarity of the non-backup-memory HTIF 
This fails in FIRRTL because <> has polarity now.
 2016-03-24 12:00:13 -07:00
Palmer Dabbelt
c989ec5813 Fix the SCR file for Chisel 3 2016-03-21 11:55:40 -07:00
Howard Mao
e90a9dfb2b make taking max of multiple integers in config a bit easier 2016-03-16 14:35:08 -07:00
Eric Love
4fc2a14a63 Fix MIF bug that cuts off upper xact id bits 2016-03-16 13:50:30 -07:00
Andrew Waterman
9dc0cbdfa4 WIP on privileged spec v1.9 2016-03-14 18:03:33 -07:00
Andrew Waterman
f2ded2721d Merge branch 'master' into add-rv32-support 2016-03-10 19:33:04 -08:00
Andrew Waterman
25091003af Add RV32 test/configuration options 
These won't actually work until further commits.  Rocket RV32 support
is complete, but on the priv-1.9 branch.
 2016-03-10 17:40:21 -08:00
Andrew Waterman
7a75a03123 tabs are evil 2016-03-10 14:18:56 -08:00
Howard Mao
3c9e63f5a5 don't make HTIF clock divider tied to backup memory 2016-03-09 14:58:20 -08:00
Howard Mao
5e145515e1 fix some Chisel assertions 2016-03-02 14:50:49 -08:00
Albert Magyar
a80b0e959d Add support for per-way cache metadata 
Adds a new cache parameter (SplitMetadata) and an associated knob.

Closes #62
 2016-03-01 13:03:24 -08:00
John Wright
ba96ad2b38 Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip 2016-02-27 16:24:45 -08:00
Palmer Dabbelt
a0f3189c74 Change MIF_DATA_BITS back to 64 
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM.  Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.

Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
 2016-02-27 11:43:44 -08:00
Palmer Dabbelt
9ea8c4e781 Add an 8-channel backup memory port config 
Now that the backup memory port works I want to test it.
 2016-02-27 10:56:13 -08:00
Palmer Dabbelt
7319f430d0 Fix the backup memory port on multiple-channel configs 
The backup memory port doesn't work on multi-channel configurations, it
just screws up the Nasti tag bits.  This patch always instantiates a
single-channel backup memory port, which relies on the memory channel
selector to only enable a single memory channel when the backup memory
port is enabled.  There are some assertions to make sure this happens,
as otherwise memory gets silently corrupted.

While this is a bit of a hack, the backup memory port will be going away
soon so I don't want to spend a whole lot of time fixing it.  The
generated hardware is actually very similar: we used to elaborate a
Nasti arbiter inside the backup memory support, now there's one outside
of it instead.
 2016-02-27 10:47:52 -08:00
Palmer Dabbelt
7c0c48fac4 Resurrect the backup memory port 
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion.  This makes a few changes:

 * Rather than calling the backup memory port parameters MEM_*, it calls
   them MIF_* (to match the MIT* paramater objects).  A new name was
   necessary because the Nasti stuff is now dumped as MEM_*, which has
   similar names but incompatible values.

 * p(MIFDataBits) was changed back to 128, as otherwise the backup
   memory port doesn't work (it only send half a TileLink transaction).
   64 also causes readmemh to bail out, but changing the elf2hex parameters
   works around that.

 * A configuration was added that enabled the backup memory port in the
   tester.  While this is kind of an awkward way to do it, I want to
   make sure I can start testing this regularly and this makes it easy to
   integrate.
 2016-02-27 10:46:56 -08:00
Yunsup Lee
a2381d2faf RoCC PTW refactoring 2016-02-25 17:26:42 -08:00
Colin Schmidt
ef4915bd2c make the asm suites ordered by their insertion order 2016-02-24 19:49:35 -08:00
Colin Schmidt
ad81d95751 add run-asm-{p,pt,v}-tests targets for convenience 2016-02-24 19:49:35 -08:00
John Wright
b04cd545b6 pass base SCR address to SCRFile for address calculation 2016-02-24 15:32:46 -08:00
Howard Mao
8a877fa620 Add Matthew Naylor's trace generator and AXE scripts 2016-02-24 14:39:11 -08:00
Howard Mao
8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
Palmer Dabbelt
c263c636b3 Actually reference all the tests from RISCV 2016-02-23 16:05:27 -08:00
Palmer Dabbelt
bae4c0c0c9 Point Testing to $RISCV/... not $base_dir/... 
This uses the compiled tests in RISCV, which match the rest of the toolchain.
 2016-02-23 10:58:51 -08:00
Colin Schmidt
4ce603e548 Memtest configs should not have a hex file loaded 2016-02-22 12:49:26 -08:00
Colin Schmidt
0c575403af only use a single asm test and 1 bmark for memtest 2016-02-22 09:36:53 -08:00
Howard Mao
5e4a02038c move FPGA AXI to HTIF converter into Chisel module 2016-02-19 13:53:31 -08:00
Palmer Dabbelt
926efd0cab Allow the number of memory channels to be picked at runtime 
We're building a chip with 8 memory channels.  Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels.  This commit adds a SCR that controls the number of active
memory channels on a chip.  Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.

By default this just adds a 1-bit SCR, which essentially no extra logic.

When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration.  The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.

A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
 2016-02-17 15:23:30 -08:00
Palmer Dabbelt
db9de94588 Generate and use SCR address header files 
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
 2016-02-17 15:23:18 -08:00
Christopher Celio
c1b4d9372f Revert "add new parameters for new SCR file" 
This reverts commit 4dad5b8b32.

The commit breaks the build.
 2016-02-13 04:02:20 -08:00
Christopher Celio
6c6bbca92a Revert "use singleton for global" 
This reverts commit 4d0f941de3.

The commit breaks the build.
 2016-02-13 03:56:47 -08:00
John Wright
4d0f941de3 use singleton for global 2016-02-13 00:56:11 -08:00
John Wright
4dad5b8b32 add new parameters for new SCR file 2016-02-12 18:24:12 -08:00
Howard Mao
9fb2216548 get rid of unused external mmio port 2016-02-10 21:49:02 -08:00
Howard Mao
72a876bfba add NASTI to TL converter 2016-02-10 11:12:39 -08:00
Palmer Dabbelt
b2ed35e8aa Print a better error on missing config classes 
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
 2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc Add a "/" when targetDir doesn't have one 
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
 2016-02-05 09:57:47 -08:00
Palmer Dabbelt
3bb0f11e6c Chisel3 <> reverse fix 2016-02-05 09:56:42 -08:00
Howard Mao
06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments 
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
 2016-02-02 13:14:52 -08:00
Howard Mao
33aa64212d fix more Chisel3 deprecations 2016-01-14 15:06:30 -08:00
Howard Mao
c06884b78c lowercase SMI to Smi 2016-01-11 17:44:10 -08:00
Howard Mao
806e40d19b implement DMA streaming functionality 2016-01-07 19:26:15 -08:00
Howard Mao
8190bf6e18 implement DMA unit 2015-12-16 21:27:48 -08:00
Howard Mao
1a272677ca more fixes to L2 cache 2015-12-16 21:06:39 -08:00
Howard Mao
560fdc19a8 add PLRU replacement option to L2 cache 2015-12-16 10:24:57 -08:00
Howard Mao
7ad9deeaee Fix issues with request merging in L2 cache and add regression tests 
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
 2015-12-15 23:02:15 -08:00
Howard Mao
0c91e00676 move GroundTest configs to a separate file 2015-12-06 03:01:05 -08:00
Howard Mao
4f5dabcda2 add SCR file to device tree 2015-12-05 00:28:58 -08:00
Howard Mao
f35b83d3ca allow configuration of rocket ICache buffering 2015-12-02 17:18:39 -08:00
Howard Mao
cdc476a370 change Rocc parameterization 2015-12-01 17:56:09 -08:00
Andrew Waterman
e0d849fec5 Fix zscale testing 
Use the following command in vsim:

make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
 2015-12-01 17:31:48 -08:00
Howard Mao
c8c68e75bb base NGenerators on NTiles, not the other way around 2015-12-01 15:26:09 -08:00
Howard Mao
40d68406d6 use xlen parameter for ALU 2015-11-30 18:04:44 -08:00
Howard Mao
23f0756978 implement support for multiple RoCC accelerators 2015-11-26 12:49:04 -08:00
Andrew Waterman
e25a020e60 Construct device tree ROM in MMIO region 
Rebuild riscv-tools for this to work!
 2015-11-25 21:23:37 -08:00
Howard Mao
ec6bfde9a3 fix WritebackUnit issue in uncore 2015-11-21 16:11:22 -08:00
Howard Mao
9d50f37289 fix unused set issue for multiple L2 cache banks 2015-11-20 23:26:28 -08:00
Howard Mao
ad3b7fd0e1 adjust CacheFillTest configuration 2015-11-19 10:52:14 -08:00
Howard Mao
4806f72b08 add CacheFillTest to check L2 conflict misses 2015-11-19 00:16:28 -08:00
Howard Mao
3514b6eb87 add some more useful configurations 2015-11-18 22:11:17 -08:00
Howard Mao
379d43d5f4 make MultiChannel routing more performant 2015-11-18 22:11:17 -08:00
Andrew Waterman
5195a5b891 Remove IPI network 
This is now provided via MMIO.
 2015-11-16 21:53:14 -08:00
Howard Mao
a1063bad54 fix issues with non-allocating put/get 2015-11-12 15:54:34 -08:00
Howard Mao
6ddf81090b didn't mean to turn off GenerateCached in last commit 2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db restore old L2 cache AcquireTransactor configuration 2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc default to single tile in WithMemtest 2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
Howard Mao
149480411e make sure ClientTileLinkEnqueuer uses the correct parameters 2015-11-10 16:09:19 -08:00
Howard Mao
51f128ec74 actually use backendBuffering in front of unwrapper/converter chain 2015-11-09 11:50:18 -08:00
Howard Mao
bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao
7b252d8f89 get rid of now-unnecessary bits in MIF tag 2015-11-05 10:48:32 -08:00
Sagar Karandikar
ee9195be26 rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity 2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b fix NSets calculation 2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Howard Mao
04d92dddbd add back decoupled NASTI connection at edge of RocketChip 2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674 add 2 and 4 memory channel configs 2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc add multichannel NASTI support in Verilog testbench 2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Howard Mao
eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect 2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de implement MultiChannel routing 2015-10-26 14:15:25 -07:00
Yunsup Lee
a175afae73 make ZscaleChip work with new parameters framework 2015-10-25 10:24:39 -07:00
Colin Schmidt
854feab08e add knob and constraint dumping 2015-10-22 17:25:38 -07:00
Henry Cook
9769b2747c now depend on external cde library rather than chisel.params (bump all submodules) 2015-10-21 18:24:16 -07:00
Howard Mao
c311c9938e nitpicky declaration move 2015-10-20 21:10:54 -07:00
Henry Cook
62765e9609 L2 rowBits param bugfix 2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale) 2015-10-20 15:05:12 -07:00
Henry Cook
8c3370c2e3 L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale) 2015-10-16 19:15:47 -07:00
Howard Mao
c4117eb9a2 make sure TL parameters change properly throughout 
* Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
 2015-10-14 18:03:39 -07:00
Henry Cook
4270fd78a5 Merge branch 'param-refactor-tl' 2015-10-14 12:16:22 -07:00
Henry Cook
dd5052888d refactor tilelink params, compiles but ExampleSmallConfig fails 2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77 add support for different TileLink and MIF data widths 2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75 added HasAddrMapParameters and GlobalAddrMap 2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1 inject params at top-level for MemDessert 2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57 Removed all traces of params 2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3 refactor MemIO to not use params 2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907 refactor NASTI to not use param; new AddrMap class 2015-10-06 11:41:47 -07:00
Andrew Waterman
79cdf6efc0 Make perf counters optional 2015-09-28 13:56:08 -07:00
Howard Mao
7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao
0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao
8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao
56ecdff52d Implement NASTI-based Mem/IO interconnect 2015-09-22 10:32:31 -07:00
Andrew Waterman
c6bcc832a1 Chisel3: Don't use Vec.fill for IOs 2015-09-20 13:43:56 -07:00
Christopher Celio
c9d89226fb Generated *.d file of tests now kept in order 
-Changed Set to LinkedHashSet in Testing.scala
 2015-09-11 18:36:04 -07:00
Andrew Waterman
700910adff Chisel3 compatibility fix for <> 2015-08-05 15:34:40 -07:00
Andrew Waterman
34b9a7fdc5 Various Chisel3 compatibility changes 2015-08-03 18:54:56 -07:00
Henry Cook
0c9a7817b6 Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7) 2015-07-30 16:30:00 -07:00