Purge legacy HTIF things

The SCR file is gone, too, because it was tightly coupled.  The
general concept could be revived as a module that somehow connects
to the debug module.

src/main/scala/Configs.scala

@@ -108,12 +108,6 @@ class BaseConfig extends Config (
     lazy val innerDataBits = site(MIFDataBits)
     lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
     pname match {
-      case HtifKey => HtifParameters(
-                       width = Dump("HTIF_WIDTH", 16),
-                       nSCR = 64,
-                       csrDataBits = site(XLen),
-                       offsetBits = site(CacheBlockOffsetBits),
-                       nCores = site(NTiles))
       //Memory Parameters
       case PAddrBits => 32
       case PgIdxBits => 12
@@ -312,7 +306,6 @@ class BaseConfig extends Config (
       case BankIdLSB => 0
       case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
       case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
-      case UseHtifClockDiv => true
       case ConfigString => makeConfigString()
       case GlobalAddrMap => globalAddrMap
       case _ => throw new CDEMatchError
@@ -413,7 +406,6 @@ class WithRV32 extends Config(
 class FPGAConfig extends Config (
   (pname,site,here) => pname match {
     case NAcquireTransactors => 4
-    case UseHtifClockDiv => false
     case _ => throw new CDEMatchError
   }
 )

src/main/scala/RocketChip.scala

@@ -31,8 +31,6 @@ case object NOutstandingMemReqsPerChannel extends Field[Int]
 /** Number of exteral MMIO ports */
 case object NExtMMIOAXIChannels extends Field[Int]
 case object NExtMMIOAHBChannels extends Field[Int]
-/** Whether to divide HTIF clock */
-case object UseHtifClockDiv extends Field[Boolean]
 /** Function for building some kind of coherence manager agent */
 case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
 /** Function for building some kind of tile connected to a reset signal */
@@ -66,11 +64,6 @@ trait HasTopLevelParameters {
   lazy val mifAddrBits = p(MIFAddrBits)
   lazy val mifDataBeats = p(MIFDataBeats)
   lazy val xLen = p(XLen)
-  lazy val nSCR =  p(HtifKey).nSCR
-  lazy val scrAddrBits = log2Up(nSCR)
-  lazy val scrDataBits = 64
-  lazy val scrDataBytes = scrDataBits / 8
-  //require(lsb + log2Up(nBanks) < mifAddrBits)
 }
 
 class MemBackupCtrlIO extends Bundle {
@@ -176,7 +169,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
 /** Wrapper around everything that isn't a Tile.
   *
   * Usually this is clocked and/or place-and-routed separately from the Tiles.
-  * Contains the Host-Target InterFace module (HTIF).
   */
 class Uncore(implicit val p: Parameters) extends Module
     with HasTopLevelParameters {

src/main/scala/Testing.scala

@@ -5,7 +5,6 @@ package rocketchip
 import Chisel._
 import scala.collection.mutable.{LinkedHashSet,LinkedHashMap}
 import cde.{Parameters, ParameterDump, Config}
-import uncore.AllSCRFiles
 
 abstract class RocketTestSuite {
   val dir: String
@@ -201,7 +200,4 @@ object TestGenerator extends App with FileSystemUtilities {
   val w = createOutputFile(configClassName + ".cst")
   w.write(world.getConstraints)
   w.close
-  val scr_map_hdr = createOutputFile(topModuleName + "." + configClassName + ".scr_map.h")
-  AllSCRFiles.foreach{ map => scr_map_hdr.write(map.as_c_header) }
-  scr_map_hdr.close
 }